Im trying to implement a jk flip flop gate level in verilog using nand gates but for some weird reason i dont get a proper output.

Here is my jk flip flop module:

module jk_flip_flop(q, q_bar, j, k, clk); output q, q_bar; input j, k, clk; wire j_star, k_star; nand(j_star, q_bar, j, clk); nand(k_star, clk, k, q); nand(q, j_star, q_bar); nand(q_bar, q, k_star); endmodule 

and this is the testbench:

module tb_jk_flip_flop(); reg j, k, clk; wire q, q_bar; initial begin j = 1; clk = 1; k = 0; #100; $display("q = %d, q_bar = %d", q, q_bar); j = 0; clk = 1; k = 1; #100; $display("q = %d, q_bar = %d", q, q_bar); j = 1; clk = 1; k = 1; #100; $display("q = %d, q_bar = %d", q, q_bar); end endmodule 

this compiles and runs successfully but gives the following output:

q = z, q_bar = z q = z, q_bar = z q = z, q_bar = z 

Please correct my code i know there is a mistake but i dont know where im wrong.

Im trying to implement a jk flip flop gate level in verilog using nand gates but for some weird reason i dont get a proper output.

Here is my jk flip flop module:

module jk_flip_flop(q, q_bar, j, k, clk); output q, q_bar; input j, k, clk; wire j_star, k_star; nand(j_star, q_bar, j, clk); nand(k_star, clk, k, q); nand(q, j_star, q_bar); nand(q_bar, q, k_star); endmodule 

and this is the testbench:

module tb_jk_flip_flop(); reg j, k, clk; wire q, q_bar; jk_flip_flop jkff(q, q_bar, j, k, clk); initial begin j = 1; clk = 1; k = 0; #100; $display("q = %d, q_bar = %d", q, q_bar); j = 0; clk = 1; k = 1; #100; $display("q = %d, q_bar = %d", q, q_bar); j = 1; clk = 1; k = 1; #100; $display("q = %d, q_bar = %d", q, q_bar); end endmodule 

this compiles and runs successfully but gives the following output:

q = x, q_bar = x q = x, q_bar = x q = x, q_bar = x 

Please correct my code i know there is a mistake but i dont know where im wrong.