Timeline for Read parallel data that is valid in falling edge clock NUCLEO-H743ZI2
Current License: CC BY-SA 4.0
4 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Sep 12, 2022 at 5:30 | comment | added | AHMED | the ADC the sampling speed that I am working with could be from 4-16MSPS. | |
| Sep 12, 2022 at 5:29 | comment | added | AHMED | thank you for the feedback Tom, actually I have 5 ADC output (2bit CH1(I0,I1) and 2bit CH2(Q0,Q1)) and 1 clk_out. I have tried to work with the DCMI I even wrote a code but it did not work. | |
| S Sep 11, 2022 at 19:50 | review | First answers | |||
| Sep 11, 2022 at 21:16 | |||||
| S Sep 11, 2022 at 19:50 | history | answered | Tom V | CC BY-SA 4.0 |