Timeline for VHDL: is this RAM design over-complicated?
Current License: CC BY-SA 4.0
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| Aug 2, 2024 at 21:30 | comment | added | user224802 | Also, I don't intend to use a FPGA, I planned to stop at the simulation stage for now. The goal was to do everything "from scratch" to understand the inner working of a RAM, without the help of FPGA hardwares. | |
| Aug 2, 2024 at 21:26 | comment | added | user224802 | Hi, you're right, it's probably due to the HDL optimization. I don't know why but shifting the addr signal by 2 confused the synthesis. The goal of this shift was to get a byte-addressable RAM instead of a word-addressable. I really don't understand what is the issue with that, for me it should work. Obviously it does not... | |
| Aug 2, 2024 at 20:29 | history | answered | Peter Green | CC BY-SA 4.0 |