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When switch is open, how come the voltage at pin is Vcc. Wouldn't it drop a bit from the pull-up resistor?

In theory, yes. In reality, current draw for a digital input will typically be something like 1 uA or less (at least with something like CMOS--with something like TTL, it'll be much higher, like 10 mA for "low" and 40 mA for "high--which is part of why you'd normally use a pull-down instead of pull-up with TTL). That being the case, the voltage drop is extremely minimal.

From a purely steady-state analysis, the pull-up resistor could be any value low enough that the voltage drop left the pin at a logic 1. Just to pick a concrete example, let's look at the specs on an ATMega:

Let's assume V_cc = 3.3 volts. So, the minimum voltage we need to maintain on the input pin is 0.7*3.3 = 2.31 volts. That means the maximum voltage drop is 3.3-2.31 volts. The maximum current draw is 1 uA.

R = E/I, so the largest resistor we could tolerate would be: (3.3-2.31)/0.000001 = 990K.

Note, however, that it actually calls for a much smaller pull-up resistor (a maximum of 50K). There are a couple of reasons for that. First of all, in real life, components have tolerances, so we don't want to require a 1% tolerance on a pull-up to assure the circuit works. Second, this isn't actually a steady state circuit. Third, the input impedance isn't pure resistance (or even close to it).

As soon as something quits pulling that input low, we want it to transition to high within a single clock cycle (or actually less). From a steady state DC viewpoint, we could look at the input pin as just a resistor to ground:

^{simulate this circuit – Schematic created using CircuitLab}

...but from an AC viewpoint with transitions between low and high voltage, it's something more like this:

^{simulate this circuit}

Let's assume we were driving this input at 20 MHz. That means our pull-up resistor has to allow enough current to flow to charge the capacitor to a "high" voltage in less than 50 ns (we'd have to look at timing diagrams to figure out how much less, but something like a quarter to half that wouldn't be too outrageous a first guess). Unfortunately, we don't know exact values for those components, though the inductor, capacitor and R1 are all "small", and R2 is "large".

Fortunately, making the pullup resistor smaller only means that when something is pulling that input low, it'll sink more current. We just need to keep the resistor large enough to keep that current "reasonable". Even with the smallest recommended pull-up resistor (20K), with V_cc = 3.3, that current = 3.3/20K = 0.165 mA (or actually less, since what's pulling it low will also have some resistance).

When switch is open, how come the voltage at pin is Vcc. Wouldn't it drop a bit from the pull-up resistor?

In theory, yes. In reality, current draw for a digital input will typically be something like 1 uA or less (at least with something like CMOS--with something like TTL, it'll be much higher, like 10 mA for "low" and 40 mA for "high--which is part of why you'd normally use a pull-down instead of pull-up with TTL). That being the case, the voltage drop is extremely minimal.

From a purely steady-state analysis, the pull-up resistor could be any value low enough that the voltage drop left the pin at a logic 1. Just to pick a concrete example, let's look at the specs in the ATmega48PB/88PB/168PB Data Sheet:

Let's assume V_cc = 3.3 volts. So, the minimum voltage we need to maintain on the input pin is 0.7*3.3 = 2.31 volts. That means the maximum voltage drop is 3.3-2.31 volts. The maximum current draw is 1 uA.

R = E/I, so the largest resistor we could tolerate would be: (3.3-2.31)/0.000001 = 990K.

Note, however, that it actually calls for a much smaller pull-up resistor (a maximum of 50K). There are a couple of reasons for that. First of all, in real life, components have tolerances, so we don't want to require a 1% tolerance on a pull-up to assure the circuit works. Second, this isn't actually a steady state circuit. Third, the input impedance isn't pure resistance (or even close to it).

As soon as something quits pulling that input low, we want it to transition to high within a single clock cycle (or actually less). From a steady state DC viewpoint, we could look at the input pin as just a resistor to ground:

^{simulate this circuit – Schematic created using CircuitLab}

...but from an AC viewpoint with transitions between low and high voltage, it's something more like this:

^{simulate this circuit}

Let's assume we were driving this input at 20 MHz. That means our pull-up resistor has to allow enough current to flow to charge the capacitor to a "high" voltage in less than 50 ns (we'd have to look at timing diagrams to figure out how much less, but something like a quarter to half that wouldn't be too outrageous a first guess). Unfortunately, we don't know exact values for those components, though the inductor, capacitor and R1 are all "small", and R2 is "large".

Fortunately, making the pullup resistor smaller only means that when something is pulling that input low, it'll sink more current. We just need to keep the resistor large enough to keep that current "reasonable". Even with the smallest recommended pull-up resistor (20K), with V_cc = 3.3, that current = 3.3/20K = 0.165 mA (or actually less, since what's pulling it low will also have some resistance).

When switch is open, how come the voltage at pin is Vcc. Wouldn't it drop a bit from the pull-up resistor?

In theory, yes. In reality, current draw for a digital input will typically be something like 1 uA or less. That being the case, the voltage drop is extremely minimal.

From a purely steady-state analysis, the pull-up resistor could be any value low enough that the voltage drop left the pin at a logic 1. Just to pick a concrete example, let's look at the specs on an ATMega:

Let's assume V_cc = 3.3 volts. So, the minimum voltage we need to maintain on the input pin is 0.7*3.3 = 2.31 volts. That means the maximum voltage drop is 3.3-2.31 volts. The maximum current draw is 1 uA.

R = E/I, so the largest resistor we could tolerate would be: (3.3-2.31)/0.000001 = 990K.

Note, however, that it actually calls for a much smaller pull-up resistor (a maximum of 50K). There are a couple of reasons for that. First of all, in real life, components have tolerances, so we don't want to require a 1% tolerance on a pull-up to assure the circuit works. Second, this isn't actually a steady state circuit. Third, the input impedance isn't pure resistance (or even close to it).

As soon as something quits pulling that input low, we want it to transition to high within a single clock cycle (or actually less). From a steady state DC viewpoint, we could look at the input pin as just a resistor to ground:

^{simulate this circuit – Schematic created using CircuitLab}

...but from an AC viewpoint with transitions between low and high voltage, it's something more like this:

^{simulate this circuit}

Let's assume we were driving this input at 20 MHz. That means our pull-up resistor has to allow enough current to flow to charge the capacitor to a "high" voltage in less than 50 ns (we'd have to look at timing diagrams to figure out how much less, but something like a quarter to half that wouldn't be too outrageous a first guess). Unfortunately, we don't know exact values for those components, though the inductor, capacitor and R1 are all "small", and R2 is "large".

Fortunately, making the pullup resistor smaller only means that when something is pulling that input low, it'll sink more current. We just need to keep the resistor large enough to keep that current "reasonable". Even with the smallest recommended pull-up resistor (20K), with V_cc = 3.3, that current = 3.3/20K = 0.165 mA (or actually less, since what's pulling it low will also have some resistance).

When switch is open, how come the voltage at pin is Vcc. Wouldn't it drop a bit from the pull-up resistor?

In theory, yes. In reality, current draw for a digital input will typically be something like 1 uA or less (at least with something like CMOS--with something like TTL, it'll be much higher, like 10 mA for "low" and 40 mA for "high--which is part of why you'd normally use a pull-down instead of pull-up with TTL). That being the case, the voltage drop is extremely minimal.

From a purely steady-state analysis, the pull-up resistor could be any value low enough that the voltage drop left the pin at a logic 1. Just to pick a concrete example, let's look at the specs on an ATMega:

Let's assume V_cc = 3.3 volts. So, the minimum voltage we need to maintain on the input pin is 0.7*3.3 = 2.31 volts. That means the maximum voltage drop is 3.3-2.31 volts. The maximum current draw is 1 uA.

R = E/I, so the largest resistor we could tolerate would be: (3.3-2.31)/0.000001 = 990K.

Note, however, that it actually calls for a much smaller pull-up resistor (a maximum of 50K). There are a couple of reasons for that. First of all, in real life, components have tolerances, so we don't want to require a 1% tolerance on a pull-up to assure the circuit works. Second, this isn't actually a steady state circuit. Third, the input impedance isn't pure resistance (or even close to it).

As soon as something quits pulling that input low, we want it to transition to high within a single clock cycle (or actually less). From a steady state DC viewpoint, we could look at the input pin as just a resistor to ground:

^{simulate this circuit – Schematic created using CircuitLab}

...but from an AC viewpoint with transitions between low and high voltage, it's something more like this:

^{simulate this circuit}

Let's assume we were driving this input at 20 MHz. That means our pull-up resistor has to allow enough current to flow to charge the capacitor to a "high" voltage in less than 50 ns (we'd have to look at timing diagrams to figure out how much less, but something like a quarter to half that wouldn't be too outrageous a first guess). Unfortunately, we don't know exact values for those components, though the inductor, capacitor and R1 are all "small", and R2 is "large".

Fortunately, making the pullup resistor smaller only means that when something is pulling that input low, it'll sink more current. We just need to keep the resistor large enough to keep that current "reasonable". Even with the smallest recommended pull-up resistor (20K), with V_cc = 3.3, that current = 3.3/20K = 0.165 mA (or actually less, since what's pulling it low will also have some resistance).

When switch is open, how come the voltage at pin is Vcc. Wouldn't it drop a bit from the pull-up resistor?

In theory, yes. In reality, current draw for a digital input will typically be something like 1 uA or less. That being the case, the voltage drop is extremely minimal.

From a purely steady-state analysis, the pull-up resistor could be any value low enough that the voltage drop left the pin at a logic 1. Just to pick a concrete example, let's look at the specs on an ATMega:

Let's assume V_cc = 3.3 volts. So, the minimum voltage we need to maintain on the input pin is 0.7*3.3 = 2.31 volts. That means the maximum voltage drop is 3.3-2.31 volts. The maximum current draw is 1 uA.

R = E/I, so the largest resistor we could tolerate would be: (3.3-2.31)/0.000001 = 990K.

Note, however, that it actually calls for a much smaller pull-up resistor (a maximum of 50K). There are a couple of reasons for that. First of all, in real life, components have tolerances, so we don't want to require a 1% tolerance on a pull-up to assure the circuit works. Second, this isn't actually a steady state circuit. Third, the input impedance isn't pure resistance (or even close to it).

As soon as something quits pulling that input low, we want it to transition to high within a single clock cycle (or actually less). From a steady state DC viewpoint, we could look at the input pin as just a resistor to ground:

^{simulate this circuit – Schematic created using CircuitLab}

...but from an AC viewpoint, it's something more like this:

^{simulate this circuit}

So let's assume we were driving this input at 20 MHz. That means our pull-up resistor has to allow enough current to flow to charge the capacitor to a "high" voltage in less than 50 ns (we'd have to look at timing diagrams to figure out how much less, but something like half that wouldn't be too outrageous a guess). Unfortunately, we don't know exact values for those components, though the inductor, capacitor and R1 are all "small", and R2 is "large".

Fortunately, making the pullup resistor smaller only means that when something is pulling that input low, it'll sink more current. We just need to keep the resistor large enough to keep that current "reasonable". Even with the smallest recommended pull-up resistor (20K), with V_cc = 3.3, that current = 3.3/20K = 0.165 mA (or actually less, since what's pulling it low will also have some resistance).

When switch is open, how come the voltage at pin is Vcc. Wouldn't it drop a bit from the pull-up resistor?

In theory, yes. In reality, current draw for a digital input will typically be something like 1 uA or less. That being the case, the voltage drop is extremely minimal.

From a purely steady-state analysis, the pull-up resistor could be any value low enough that the voltage drop left the pin at a logic 1. Just to pick a concrete example, let's look at the specs on an ATMega:

Let's assume V_cc = 3.3 volts. So, the minimum voltage we need to maintain on the input pin is 0.7*3.3 = 2.31 volts. That means the maximum voltage drop is 3.3-2.31 volts. The maximum current draw is 1 uA.

R = E/I, so the largest resistor we could tolerate would be: (3.3-2.31)/0.000001 = 990K.

Note, however, that it actually calls for a much smaller pull-up resistor (a maximum of 50K). There are a couple of reasons for that. First of all, in real life, components have tolerances, so we don't want to require a 1% tolerance on a pull-up to assure the circuit works. Second, this isn't actually a steady state circuit. Third, the input impedance isn't pure resistance (or even close to it).

As soon as something quits pulling that input low, we want it to transition to high within a single clock cycle (or actually less). From a steady state DC viewpoint, we could look at the input pin as just a resistor to ground:

^{simulate this circuit – Schematic created using CircuitLab}

...but from an AC viewpoint with transitions between low and high voltage, it's something more like this:

^{simulate this circuit}

Let's assume we were driving this input at 20 MHz. That means our pull-up resistor has to allow enough current to flow to charge the capacitor to a "high" voltage in less than 50 ns (we'd have to look at timing diagrams to figure out how much less, but something like a quarter to half that wouldn't be too outrageous a first guess). Unfortunately, we don't know exact values for those components, though the inductor, capacitor and R1 are all "small", and R2 is "large".

Fortunately, making the pullup resistor smaller only means that when something is pulling that input low, it'll sink more current. We just need to keep the resistor large enough to keep that current "reasonable". Even with the smallest recommended pull-up resistor (20K), with V_cc = 3.3, that current = 3.3/20K = 0.165 mA (or actually less, since what's pulling it low will also have some resistance).