Timeline for Buffer / Connector Topology for Daisy Chained SPI Signal Between PCBs
Current License: CC BY-SA 4.0
17 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Feb 16 at 18:40 | vote | accept | Emmett Palaima | ||
| Feb 10 at 21:02 | answer | added | bobflux | timeline score: 2 | |
| Feb 10 at 19:26 | history | edited | Emmett Palaima | CC BY-SA 4.0 | Clarifying the parameters and focusing the scope of the question |
| Feb 10 at 19:20 | history | undeleted | Emmett Palaima | ||
| Feb 10 at 4:46 | history | deleted | Emmett Palaima | via Vote | |
| Feb 9 at 17:03 | history | edited | Emmett Palaima | CC BY-SA 4.0 | edited body |
| Feb 9 at 17:03 | comment | added | Emmett Palaima | @Justme apologies, I meant SN74HCS125 | |
| Feb 9 at 16:59 | comment | added | Emmett Palaima | @Kartman breaking down the design into different components: It seems like if the SPI signal can make it through one differential cable transfer it can make it through all of them. it's purely high or low and these boards will all have their own power so it's not like it's getting noisier or anything. So if this works for the first transfer between boards it will work for all of them. The main issue to me seems to be potential for phase shift in the clock versus the data signals over time, but I'm not sure what specifically would cause this, since all the signals are getting delayed together | |
| Feb 9 at 16:52 | comment | added | Emmett Palaima | @Kartman the buffering and differential encoding wouldn't address that? | |
| Feb 9 at 16:51 | comment | added | Emmett Palaima | @TimWilliams I'm confirming the schematic before making the PCB layout. The connecters will be RJ45 jacks and the cable will be shielded Cat6, mostly short runs < 12 in | |
| Feb 9 at 16:47 | history | edited | Emmett Palaima | CC BY-SA 4.0 | MHz, Adding Schematic Image |
| Feb 9 at 13:58 | comment | added | Kartman | Bad idea on many fronts. Signal integrity, clock skew, ground bounce etc. you might want to look at Manchester encoding the data or maybe Ethercat. | |
| Feb 9 at 11:15 | comment | added | Justme | There's no schematic. And contrary to what you say, the SN74LVC125 isn't a Schmitt Trigger. | |
| Feb 9 at 11:05 | comment | added | Tim Williams | Please also include proposed PCB layout, and how the cable will be terminated (physically: connector system, type and lead dress). | |
| Feb 9 at 10:44 | comment | added | Amit M | Control several thousand shift registers in SPI daisy chain with a 100 MHz clock? Are you sure you wont have signal integrity problems? What about reflections? | |
| Feb 9 at 8:05 | comment | added | Marcus Müller | Do you really mean millihertz (mHz), or do you maybe mean Megahertz (MHz)? Capitalization really matters for physical units… | |
| Feb 9 at 7:12 | history | asked | Emmett Palaima | CC BY-SA 4.0 |