Timeline for Buffer / Connector Topology for Daisy Chained SPI Signal Between PCBs
Current License: CC BY-SA 4.0
8 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Feb 16 at 18:40 | vote | accept | Emmett Palaima | ||
| Feb 13 at 14:49 | comment | added | bobflux | It's never exactly the same because the paths are not perfectly matched, for example in Cat5 the twist rate is different between pairs, different circuits on the same chip (like the multichannel LVDS chip) are never exactly the same, etc. | |
| Feb 13 at 10:46 | comment | added | Emmett Palaima | Okay what I am asking is that since the signal is passing through the same chips at all stages, and the same length of cable, which I assume would impose the same propagation delay, wouldn't propagation delay be the same for all signals? At what point in the design does the skew arrise? | |
| Feb 11 at 23:54 | comment | added | bobflux | It is correct that delay isn't an issue. Skew is the difference in propagation delay between related signals, and that is an issue. | |
| Feb 11 at 23:33 | comment | added | Emmett Palaima | as for the skew issue, any delays imposed by cabling and buffering are being applied to all signals equally, so I wouldn't think that would cause a phase issue. Each signal would just be delayed by the same amount between boards. Is there a reason this view is inaccurate? | |
| Feb 11 at 2:12 | comment | added | Emmett Palaima | You are correct, decoupling caps will be present but not shown in the schematic snippet | |
| Feb 11 at 2:12 | comment | added | Emmett Palaima | This is an extremely helpful answer, thank you! | |
| Feb 10 at 21:02 | history | answered | bobflux | CC BY-SA 4.0 |