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If using transistors, below is a way to reduce the Vdrop across Rsense.

Executive summary:

• Shutdown condition is approx 128mV across \$R_{SENSE}\$
• Please be aware that this is not a precision circuit.

General idea:

• Let's consider the P-mos shut-down condition. It happens when the entire 3mA current is diverted by the PNP on the left.
• With the two PNP's having equal base voltage, it means the ratio of their \$I_C\$, which we choose, determines a predictable difference of their \$V_E\$. Something like 28mV near room temp based on this 3:1 current ratio.
• The 33 ohm adds an additional offset of 100mV, to desensitize us partially vs temperature (though at the expense of picking up dependence on that nominally 3mA current value).
• The shutdown condition is thus 100mV + 28mV = 128mV across \$R_{SENSE}\$. So you would scale this resistor value accordingly, to obtain the current limit into the P-mos.

The zener or TVS diode is just to protect the P-mos gate from being pulled down to \$V_{GS} = -28V\$ which is usually too much.

The transistors should be a matched pair package such as DMMT3906

Next we'll construct the bias currents simply as resistors. Here there is sensitivity to the P-mos gate voltage (when the P-mos is close to off), which I guessed at. That voltage isn't too predictable, and this is one of several things making the circuit a crude solution. An additional transistor pair could be added to stabilize the \$I_C\$ ratio but let's not complicate things.

Finally, the variant with foldback:

This one is slightly different in purpose and behavior. The reference leg of the transistor circuit is connected instead so that its bias current comes from the drain of the P-mos. This might make sense if the limiting scenario is something like an inrush, and the purpose of the protection is to stop the P-mos getting blown out. The current limit will vary pretty dramatically vs load voltage. It's probably necessary to make sure the current limit never goes all the way to zero (esp at low load voltages, near the start of an inrush), which can happen for some resistor value combinations when tweaking it. I would also be quite cautious about reproducibility of something like this - i.e. leave plenty of margin for error. Graphs: green=load-voltage 0-27V ramp; white=P-mos power dissipation

If using transistors, below is a way to reduce the Vdrop across Rsense.

Executive summary:

• Shutdown condition is approx 128mV across \$R_{SENSE}\$
• Please be aware that this is not a precision circuit.

General idea:

• Let's consider the P-mos shut-down condition. It happens when the entire 3mA current is diverted by the PNP on the left.
• With the two PNP's having equal base voltage, it means the ratio of their \$I_C\$, which we choose, determines a predictable difference of their \$V_E\$. Something like 28mV near room temp based on this 3:1 current ratio.
• The 33 ohm adds an additional offset of 100mV, to desensitize us partially vs temperature (though at the expense of picking up dependence on that nominally 3mA current value).
• The shutdown condition is thus 100mV + 28mV = 128mV across \$R_{SENSE}\$. So you would scale this resistor value accordingly, to obtain the current limit into the P-mos.

The zener or TVS diode is just to protect the P-mos gate from being pulled down to \$V_{GS} = -28V\$ which is usually too much.

The transistors should be a matched pair package such as DMMT3906

Next we'll construct the bias currents simply as resistors. Here there is sensitivity to the P-mos gate voltage (when the P-mos is close to off), which I guessed at. That voltage isn't too predictable, and this is one of several things making the circuit a crude solution. An additional transistor pair could be added to stabilize the \$I_C\$ ratio but let's not complicate things.

Finally, a variant with foldback:

• This one is slightly different in purpose and behavior.
• The scenario this is for might be if something like an inrush, and the purpose of the protection would be to stop the P-mos getting blown out. Thus we would be more interested in power into the P-mos, rather than current. The current limit will thus vary substantially vs load voltage.
• The power-vs-voltage curve can be shaped by tweaking resistor values
• general idea of the circuit: Compared to the previous circuit, here the reference leg of the PNP comparator (the one with 27k) is connected instead so that its bias current comes (mostly) from the drain of the P-mos. (An additional resistor to ground, 680k here, lets it continue limiting when the load voltage is near the supply.)
• It's probably necessary to make sure the current limit never goes all the way to zero (esp at low load voltages, near the start of an inrush), which can happen for some resistor value combinations when tweaking it.
• I would be extra cautious about reproducibility of something like this - i.e. leave plenty of margin for error. (click to zoom)

If using transistors, below is a way to reduce the Vdrop across Rsense.

Executive summary:

• Shutdown condition is approx 128mV across \$R_{SENSE}\$
• Please be aware that this is not a precision circuit.

General idea:

• Let's consider the P-mos shut-down condition. It happens when the entire 3mA current is diverted by the PNP on the left.
• With the two PNP's having equal base voltage, it means the ratio of their \$I_C\$, which we choose, determines a predictable difference of their \$V_E\$. Something like 28mV near room temp based on this 3:1 current ratio.
• The 33 ohm adds an additional offset of 100mV, to desensitize us partially vs temperature (though at the expense of picking up dependence on that nominally 3mA current value).
• The shutdown condition is thus 100mV + 28mV = 128mV across \$R_{SENSE}\$. So you would scale this resistor value accordingly, to obtain the current limit into the P-mos.

The zener or TVS diode is just to protect the P-mos gate from being pulled down to \$V_{GS} = -28V\$ which is usually too much.

Next we'll construct the bias currents simply as resistors. Here there is sensitivity to the P-mos gate voltage (when the P-mos is close to off), which I guessed at. That voltage isn't too predictable, and this is one of several things making the circuit a crude solution. An additional transistor pair could be added to stabilize the \$I_C\$ ratio but let's not complicate things.

Finally, the variant with foldback:

This one is slightly different in purpose and behavior. The reference leg of the transistor circuit is connected instead so that its bias current comes from the drain of the P-mos. This might make sense if the limiting scenario is something like an inrush, and the purpose of the protection is to stop the P-mos getting blown out. The current limit will vary pretty dramatically vs load voltage. It's probably necessary to make sure the current limit never goes all the way to zero (esp at low load voltages, near the start of an inrush), which can happen for some resistor value combinations when tweaking it. I would also be quite cautious about reproducibility of something like this - i.e. leave plenty of margin for error. Graphs: green=load-voltage 0-27V ramp; white=P-mos power dissipation

If using transistors, below is a way to reduce the Vdrop across Rsense.

Executive summary:

• Shutdown condition is approx 128mV across \$R_{SENSE}\$
• Please be aware that this is not a precision circuit.

General idea:

• Let's consider the P-mos shut-down condition. It happens when the entire 3mA current is diverted by the PNP on the left.
• With the two PNP's having equal base voltage, it means the ratio of their \$I_C\$, which we choose, determines a predictable difference of their \$V_E\$. Something like 28mV near room temp based on this 3:1 current ratio.
• The 33 ohm adds an additional offset of 100mV, to desensitize us partially vs temperature (though at the expense of picking up dependence on that nominally 3mA current value).
• The shutdown condition is thus 100mV + 28mV = 128mV across \$R_{SENSE}\$. So you would scale this resistor value accordingly, to obtain the current limit into the P-mos.

The zener or TVS diode is just to protect the P-mos gate from being pulled down to \$V_{GS} = -28V\$ which is usually too much.

The transistors should be a matched pair package such as DMMT3906

Next we'll construct the bias currents simply as resistors. Here there is sensitivity to the P-mos gate voltage (when the P-mos is close to off), which I guessed at. That voltage isn't too predictable, and this is one of several things making the circuit a crude solution. An additional transistor pair could be added to stabilize the \$I_C\$ ratio but let's not complicate things.

Finally, the variant with foldback:

This one is slightly different in purpose and behavior. The reference leg of the transistor circuit is connected instead so that its bias current comes from the drain of the P-mos. This might make sense if the limiting scenario is something like an inrush, and the purpose of the protection is to stop the P-mos getting blown out. The current limit will vary pretty dramatically vs load voltage. It's probably necessary to make sure the current limit never goes all the way to zero (esp at low load voltages, near the start of an inrush), which can happen for some resistor value combinations when tweaking it. I would also be quite cautious about reproducibility of something like this - i.e. leave plenty of margin for error. Graphs: green=load-voltage 0-27V ramp; white=P-mos power dissipation

If using transistors, below is a way to reduce the Vdrop across Rsense.

Executive summary:

• Shutdown condition is approx 128mV across \$R_{SENSE}\$
• Please be aware that this is not a precision circuit.

General idea:

• Let's consider the P-mos shut-down condition. It happens when the entire 3mA current is diverted by the PNP on the left.
• With the two PNP's having equal base voltage, it means the ratio of their \$I_C\$, which we choose, determines a predictable difference of their \$V_E\$. Something like 28mV near room temp based on this 3:1 current ratio.
• The 33 ohm adds an additional offset of 100mV, to desensitize us partially vs temperature (though at the expense of picking up dependence on that nominally 3mA current value).
• The shutdown condition is thus 100mV + 28mV = 128mV across \$R_{SENSE}\$. So you would scale this resistor value accordingly, to obtain the current limit into the P-mos.

The zener or TVS diode is just to protect the P-mos gate from being pulled down to \$V_{GS} = -28V\$ which is usually too much.

Next we'll construct the bias currents simply as resistors. Here there is sensitivity to the P-mos gate voltage (when the P-mos is close to off), which I guessed at. That voltage isn't too predictable, and this is one of several things making the circuit a crude solution. An additional transistor pair could be added to stabilize the \$I_C\$ ratio but let's not complicate things.

Finally, the variant with foldback:

This one is slightly different in purpose and behavior. The right leg of the transistor circuit is connected instead to the drain of the P-mos. This might make sense if the limiting scenario is something like an inrush, and the purpose of the protection is to stop the P-mos getting blown out. The current limit will vary pretty dramatically vs load voltage. It's probably necessary to make sure the current limit never goes all the way to zero (esp at low load voltages, near the start of an inrush), which can happen for some resistor value combinations when tweaking it. I would also be quite cautious about reproducibility of something like this - i.e. leave plenty of margin for error. Graphs: green=load-voltage 0-28V ramp; white=P-mos power dissipation

If using transistors, below is a way to reduce the Vdrop across Rsense.

Executive summary:

• Shutdown condition is approx 128mV across \$R_{SENSE}\$
• Please be aware that this is not a precision circuit.

General idea:

• Let's consider the P-mos shut-down condition. It happens when the entire 3mA current is diverted by the PNP on the left.
• With the two PNP's having equal base voltage, it means the ratio of their \$I_C\$, which we choose, determines a predictable difference of their \$V_E\$. Something like 28mV near room temp based on this 3:1 current ratio.
• The 33 ohm adds an additional offset of 100mV, to desensitize us partially vs temperature (though at the expense of picking up dependence on that nominally 3mA current value).
• The shutdown condition is thus 100mV + 28mV = 128mV across \$R_{SENSE}\$. So you would scale this resistor value accordingly, to obtain the current limit into the P-mos.

The zener or TVS diode is just to protect the P-mos gate from being pulled down to \$V_{GS} = -28V\$ which is usually too much.

Next we'll construct the bias currents simply as resistors. Here there is sensitivity to the P-mos gate voltage (when the P-mos is close to off), which I guessed at. That voltage isn't too predictable, and this is one of several things making the circuit a crude solution. An additional transistor pair could be added to stabilize the \$I_C\$ ratio but let's not complicate things.

Finally, the variant with foldback:

This one is slightly different in purpose and behavior. The reference leg of the transistor circuit is connected instead so that its bias current comes from the drain of the P-mos. This might make sense if the limiting scenario is something like an inrush, and the purpose of the protection is to stop the P-mos getting blown out. The current limit will vary pretty dramatically vs load voltage. It's probably necessary to make sure the current limit never goes all the way to zero (esp at low load voltages, near the start of an inrush), which can happen for some resistor value combinations when tweaking it. I would also be quite cautious about reproducibility of something like this - i.e. leave plenty of margin for error. Graphs: green=load-voltage 0-27V ramp; white=P-mos power dissipation