Timeline for PLL not locking after CPLD change
Current License: CC BY-SA 4.0
10 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Nov 13 at 13:02 | history | rollback | Velvet | Rollback to Revision 2 | |
| Nov 13 at 12:52 | comment | added | Chester Gillon | Why was the question edited to remove the "old" VHDL code? With the question containing only the "new" VHDL code doesn't seem to make sense and might have invalidated the answer already given. | |
| Nov 13 at 12:43 | history | edited | G.J. | CC BY-SA 4.0 | deleted 2439 characters in body |
| Nov 13 at 7:17 | history | edited | G.J. | CC BY-SA 4.0 | deleted 147 characters in body |
| Nov 8 at 3:03 | review | Close votes | |||
| Nov 18 at 3:01 | |||||
| Nov 3 at 11:53 | answer | added | ocelot | timeline score: 1 | |
| Nov 3 at 11:29 | review | Close votes | |||
| Nov 3 at 15:16 | |||||
| Nov 3 at 11:11 | history | edited | G.J. | CC BY-SA 4.0 | added 64 characters in body |
| S Nov 3 at 10:54 | review | First questions | |||
| Nov 3 at 15:09 | |||||
| S Nov 3 at 10:54 | history | asked | G.J. | CC BY-SA 4.0 |