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Aug 4, 2013 at 21:59 vote accept Jonathon Reinhart
Aug 4, 2013 at 21:58 comment added Jonathon Reinhart This seems to be working for my isolated test. Now I'm having trouble applying those constraints for a EDK custom core. See my new question, if you or Joe Hass are knowledgeable on the topic. electronics.stackexchange.com/questions/78001/…
Aug 4, 2013 at 21:21 comment added Jonathon Reinhart First-year masters program. But honestly, the professor never mentioned any of this. I knew that I somehow had to tell the tools "hey don't worry about the timing on this path", but wasn't sure how to do it. I think I managed to get it working with False Path (before you told me not to :-) ), but I am going through this tutorial now. Thanks for your help so far.
Aug 4, 2013 at 21:13 comment added Vasiliy The documentation of the tool you're using will surely cover the topic of MCPs. Maybe it won't cover all, but it will definitely be enough
Aug 4, 2013 at 21:11 comment added Vasiliy Are you undergrad? I've never heard about undergrad courses having such a complex and interesting assignments!
Aug 4, 2013 at 21:09 comment added Jonathon Reinhart I will certainly go and research this "Multi-cycle-path" option. If anyone has any quick pointers they'd be willing to share, I'd greatly appreciate it as I've spent days on this issue.
Aug 4, 2013 at 21:08 comment added Jonathon Reinhart "Multi-cycle-path" was the term I was looking for -- we were never taught any of this, and I'm not sure it was apparent that this would come up. A suggestion to Disable the "Treat timing closure failure as error" option was made, but that sounds like a Bad Idea (tm).
Aug 4, 2013 at 20:53 comment added Joe Hass +1 Yes, the Xilinx tools will let you specify a multi-cycle constraint and that is the right way to handle this situation. The details are well documented by Xilinx.
Aug 4, 2013 at 20:51 history answered Vasiliy CC BY-SA 3.0