I am trying to implement a fixed delay line using carry chain inside FPGA (Microchip's IGLOO2). Currently one of the constraints in this project is to use carry chain as delay elements (not any other method). I tried it using full adders: in a "for...generate" statement, when index is 0 the first carry element (full adder) is generated, and when the index is greater than 0, the next element is generated, whose carry input is the output carry of the previous element. One other condition is to make sure that synthesis does not change the components (full adders stay as I defined them). Here is my code. I am pretty sure that there are a bunch of things wrong with this code, but I am still learning vhdl and currently have no idea how to implement the delay line using carry chains.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity student is generic( LENGTH : integer := 10; DATA_WIDTH : integer :=16; ); port( A : in std_logic_vector(15 downto 0); B : in std_logic_vector(15 downto 0); SUM : out std_logic_vector(15 downto 0); CIN : in std_logic; CO : out std_logic ); end entity; architecture rtl of student is signal temp : std_logic_vector(15 downto 0); signal temp1 : std_logic_vector(15 downto 0); signal temp2 : std_logic_vector(15 downto 0); signal temp3 : std_logic_vector(15 downto 0); begin abc: for i in 0 to LEGNTH-1 generate first: if i=0 generate temp1 <= '1' & A; temp2 <= '1' & B; temp <= std_logic_vector(unsigned(temp1) + unsigned(temp2)); SUM <= temp(3 downto 0); CIN <= '0'; CO <= temp(4); end generate; next: if i>0 generate temp1 <= '1' & A; temp2 <= '1' & B; temp3 <= std_logic_vector(unsigned(temp1) + unsigned(temp2)); SUM <= temp3(14 downto 0); temp3(15) <= temp(4); CIN <= temp(4); CO <= CIN; end generate; end rtl; ``` 