Construct a post-equalizing circuit to compensate imperfect of the DAC

The output signal level from any DAC has a constant RMS value until the input signal's frequency is half the sample rate - then aliasing begins because the first image and the desired output start to align.

The RMS level remains constant but, as the input sinewave becomes sampled fewer times per cycle, the DAC output waveform progressively contains more high-frequency sampling artifacts. Because the RMS is constant, the fundamental of the sinewave must reduce as f approaches half-sample-rate. This is what happens: -

All DACs do this; most of us have seen the shape of the signal as f approaches \$\dfrac{f_S}{2}\$: -

If you totalized the squares of all the samples over the period in which they align (for convenience) then divided by the number of samples then took the square root you would find that the RMS is 0.7071 i.e. exactly the same as the original analogue sinewave but it contains energy from the first image and possibly higher order images as well.

RMS = \$\sqrt{\dfrac{(+0.7071)^2 + (0)^2 + (-0.7071)^2 + (1)^2 + (-0.7071)^2 + (0)^2 + (+0.7071)^2 + (-1)^2}{8}}\$

= \$\sqrt{\dfrac{4}{8}}\$ = 0.7071 i.e. same as a sinewave of peak amplitude 1

So, to counter this effect you can add what is called a "sinc-compensation filter" to the output of the DAC - the filter attempts to reduce the falling amplitude of the fundamental by countering the formula shown on the top diagram.

To design a filter (example shown in the OP's question) you need to know the sampling rate that the system is using and adjust the value of C appropriately. Here's the full picture: -

The picture informs us that the sampling frequency is 10MHz and, if the sampling frequency for the OP's system was 100MHz then C would reduce to 8.2pF BUT don't uderestimate the effects that the op-amp can cause and, without knowing the precise sampling frequency used it is pointless trying to design and test a compensation system.