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I am planning a project that will have many ATTiny chips connected together. The idea is that a master node will send various control signals that every slave node will listen to. My system could potentially grow to several hundred nodes.

I am a little worried that if I add too many slave nodes listening to the same output pin, that the current requirements will start causing problems with the master node not being able to drive enough current.

How many chips can be connected to the same output pin before I have problems? What specs should I look for to help me know the limits?

I will specifically be using ATTiny2313 at 5v.

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    \$\begingroup\$ Your problem is not the number of connected inputs, but the length (capacitance/impedance) of the wires connecting them all together. \$\endgroup\$ Commented Jul 17, 2014 at 5:45
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    \$\begingroup\$ @CMP In theory, a high impedance digital input pulls very little current. So, the 10mA or so that an output pin can source and sink is more than enough to drive 100x high impedance inputs. In practice, there are these questions. (1) What's the nature of the signals? Is it just a logic level high/low? (2) Is it PWM? If so, what's the frequency? (3) Is it some type of communication bus? If so, what type of bus it is? What's the desired data rate? (4) What will be the physical size of the system? What kind of environment will it operate in? \$\endgroup\$ Commented Jul 17, 2014 at 6:09
  • \$\begingroup\$ All are pretty simple signals, high/low bit banging. Most demanding is probably a synchronization clock around 5kHz. All listeners will use internal pull ups. \$\endgroup\$ Commented Jul 17, 2014 at 6:12
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    \$\begingroup\$ Those internal pull-ups will require much more current than the inputs themselves. Consult the datasheet to find out how much current. \$\endgroup\$ Commented Jul 17, 2014 at 6:58
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    \$\begingroup\$ I wouldn't enable the internal pull-ups at all or just use a single external high value pull-up as you probably actively drive the signal low/high at all times anyway. \$\endgroup\$ Commented Oct 15, 2014 at 9:34

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Some important specs I got from the Attiny datasheet sectiosn 21.1 an 21.2 is that dc current per i/o pin is 40mA. Only a few pins can operate at this limit at any given time, check out the electrical characteristics its very useful.

Just for fun, let's say every device you want to drive is another attiny, from the datasheet we see maximum input leakage (low or high) is 1uA. So exceeding the 40mA per pin would be highly unlikely. As other said the real concern is how LC losses for high freqeuency signals.

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As jippie said, you have to care about line capacitance. But how do you plan to connect your slaves? Is it I2C (pull-up driven protocol) or a push-pull GPIO bit-banged protocol?

If you use I2C, take a look at the I2C specification from Phillips (Now NXP). There is a small thumb formula that kind of things to help you estimate the pull-up you should be using.

If you are using a push-pull solution (SPI, UART, bit-bang) without pull-ups, your MCU may not drive enough current (insufficient fan-out) to drive all of your slaves. In such case, you have to look for a transistor based solution or a better protocol. We need more information to help you, though.

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