Here is the circuit you are asking about:
The complaint is asymmetrical rise and fall times, but there are other issues too.
First, the slow rise time and fast fall times are exactly what should be expected from this circuit. This is because the LM311 has a open collector output. That means it actively drives the output low, but it is up to the external circuit to drive it high. That can be convenient for level shifting, but results in asymmetric rise and fall times.
There is a lower impedance driving the signal low than driving it high. With the same capacitance on the line, the time constant is longer going high than low.
The fix is to use a comparator or opamp with symmetric output drive. These will drive to the power rails of the device, so now you have to change the opamp power strategy.
Since you want a 0-5 V digital signal out, I'd start with a opamp that can run from 5 V and has rail to rail output. There are many to chose from. One example is the MCP6021. It has complementary CMOS output, 500 µV offset, and goes to 10 MHz.
Now you have to figure out how to keep the input signals within the opamp's valid range, which is 0-5 V for the MCP6021 running from 5 V. With the -15 V supply and 24 V Zeners, the nominal signal levels are at 9 V. You want those to be about 2.5 V intead. One possibility is to use a -21.5 V supply instead of the -15 V supply. This is no longer powering the opamp, just the bottom of the Zeners, so doesn't need much current capability at all. A charge pump can do this.
For extra credit, you could even control the charge pump closed loop to try to keep the average of the two signals close to 2.5 V.
A possibly better alternative is to flip the input around with the bottom ends of R1 and R2 tied to ground and the top ends to the anodes of the Zeners. Now you only need to make a positive 26.5 V or so. Again the current is so low that a filtered charge pump from the +15 V supply can do this easily.
Added
AC coupling the two inputs alleviates the need for any new supplies. You already have +15, +5, and -15 volts available. With AC coupling, that's all you need:
R1 and R2 form a voltage divider to make half of the opamp supply. C2 reduces noise on that node. I know this is a noise generator, but the kind of noise on the 5 V supply is not likely to be random. R5 and R6 DC couple this midpoint voltage to both opamp inputs. This coupling is deliberately high impedance to minimally interfere with the AC component on the opamp inputs.
R3, R4, D1, and D2 are your avalanche breakdown noise sources as before. C3 and C4 couple the AC components of that noise to the opamp inputs.
With the values shown, the high pass filter rolloff is about 160 mHz. That means the result isn't truly random in that very long term continuously high or low sequences will get truncated. However, at such low frequencies there are other sources of error anyway.
Random bit stream generation
You don't say what your application is, but most likely trying to get every last bit of true randomness from the circuit is missing the point. Usually the electronic random noise generator is followed by a digital hash function.
A CRC generator is a good example. A 32 bit CRC is a good pseudo-random generator. Unless you look at very long sequences where the limited 232 states becomes relevant, sequence snippets are pretty much indistinguishable from truly random signals. All you need is to give the CRC a occasional random kick, and the result becomes basically truly random.
In this case, every time you want a new random bit, feed the threshold-detected result of this circuit into the CRC and use the bit shifted off the end. Even if this circuit were to have correlation or other patterns over a few bits, the CRC will hash those in the short term. The randomness of the circuit will cover up the non-randomness of the CRC in the long term.
