compiling vhdl code

Question

I have a source code written in VHDL wich is intended to make an FPGA communicate witch PC via UART and a 8051 microcontroller at the same time the FPGA will be connected to 8051 via data,adresse lines, P3 (for output) the author of source code says

"The code is a simple state machine" but there is no description of wich FPGA I/O will be connected to wich PC/8051 pin (UART, data lines...) I have actel proasic3 fpga ,

do i only need to create constraint file for I/O and clock frequency in order to compile the code ? also i have a 1mb flash memory to be connected to FPGA for code storing ,does it also need a constraint file or its connection are specific ?

source code is here http://txt.do/d4xr1

Where did you get this code from? Any other documentation available (schematics, PCB layout etc.)? — Bruce Abbott
– Bruce Abbott, Commented Oct 18, 2017 at 15:06

matryx · Accepted Answer · 2017-10-18 17:06:51Z

Yes. You need to provide the IO constraints for the FPGA pads if your board has to work as expected. You will have to extract these IO pad details from the schematics of the board you are using. Also provide a period constraint for the clock as the fundamental timing constraint.

Refer http://coredocs.s3.amazonaws.com/Libero/11_8_0/Tool/des_constraints_ug.pdf for providing constraints in Libero SoC tool.

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