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I am trying to design a relay-based data latch circuit with the fewest possible relays (not just building separate logic gates and string them together, which results in lots of redundancy), under the following constraints:

  • The output must be driven to high voltage or driven to low voltage / ground, not floating.
  • I should be able to string together a bunch of modules on the same power and ground rails without them interfering with each other.
  • The output should be identical to the data line when enabled, and retain the last state of the last state of the data line when disabled.
  • The enable line can function as on-high/off-low or on-low/off-high--either way is fine, as I can just swap the labels on two switch positions.
  • The latch should operate on a 12v power supply.

I think this should be fairly easy with SPDT bistable latching relays--the output would be the common terminal of the latching relay, the switched terminals would connect to power and ground, a normal DPDT relay would connect the data line and inverse data line to the coil of the latching relay, disconnecting the data lines would leave it latched, and switching the data line between high and low while connected would change the direction of current flow in the latching relay, changing its state.

However, I would like to use transparent-case components, preferably with built-in indicator lights, for the sake of making it easy to inspect the system state, and I haven't been able to find bistable latching relays that fit that description. So, is there a simple way to do this with just regular non-latching SPDT relays? (And possibly some resistors and/or diodes? Or is there a good source for polarity-sensitive bistable latching relays that would meet my visibility needs?)

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  • \$\begingroup\$ Compared to all-electronic circuits, there is a significant delay between switching a current into a relay coil and the armature moving enough to change the output state. Mitigating race conditions probably will increase the body count. \$\endgroup\$ Commented Feb 24 at 22:09
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    \$\begingroup\$ FYI, There used to be something called switching theory, mostly invented by the people who built the first automated telephone switching systems, that was all about designing digital logic based on relatively expensive switches (e.g., relays or vacuum tubes) and cheap interconnects (copper wire.) That's the exact opposite of designing logic for integrated circuits, where the switches (transistors) are cheap, and the interconnects (metalization) are expensive. \$\endgroup\$ Commented Feb 24 at 22:58
  • \$\begingroup\$ @AnalogKid Hence the desire for easily-inspectable components. But the relays will not be switched frequently, so I don't expect race conditions to be much of a problem. \$\endgroup\$ Commented Feb 24 at 23:14
  • \$\begingroup\$ A race condition affects how quickly a system stabilizes after a change of state, and even whether or not it ever stabilizes. In your case, it is independent of how often the system changes state. \$\endgroup\$ Commented Feb 25 at 3:44
  • \$\begingroup\$ What components are allowed. only relays? \$\endgroup\$ Commented Feb 25 at 6:21

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I have been playing with these on and off for couple of years now (just as a puzzle, without any project in mind). The best I've been able to come up with is a D type level triggered latch with single SPDT relay and four diodes and a D type edge triggered flip-flop with two SPDT relays and five diodes:

Schematic

Falstad link

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Have a look at the work of Simon Winder, whose marvelous Calculating Engine does square roots, and uses 480 relays, arranged in a subunit he calls the DFLIP. Each uses three 4PCO relays (for standardisation), but as you can see from his diagram below, you could use DPDT relays, obviously with built-in LEDs if you wanted. I think his circuit fits your needs exactly.

Calculating Engine

DFLIP Sub Unit
One of the innovations that made this relay machine possible was the development of an edge triggered D-type flip flop. I think this is possibly a unique circuit invention. The challenge with relays vs digital logic is that it is hard to overcome the intermediate state as a relay switches from the normally closed contacts over to the normally open ones. During this state, nothing is connected, and so it is quite difficult to build anything that is like synchronous logic. However I managed to invent a positive edge triggered D-type flip flop using three relays which forms the basis for a number of the registers and counters in this machine [...] Looking at the schematic one can see that there are two input relays (S and R) and one output (Q) relay. The S input relay is for setting the Q relay and the R input relay for resetting it. Continues...

enter image description here
From https://web.archive.org/web/20181004065941/http://simonwinder.com/wp-content/uploads/2014/05/dflip.png The Normally-Open contacts are closest to the coils.

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  • \$\begingroup\$ I need a level-enabled latch, rather than an edge-triggered flipflop, but that's a start, at least! \$\endgroup\$ Commented Feb 26 at 18:52
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I believe I have figured it out. A single bit requires two relays (and a capacitor and 3 diodes); storing more bits with a shared enable line allows reducing the average relays per bit; using, for example, a 4PCO relay for the enable line would allow storing 4 bits with 5 relays (and 4 capacitors and 9 diodes).

The key insight, as captured in the diagram on the right, is that a data latch is essentially a two-line multiplexer with the output feeding back into one of the inputs. The enable line switches the output between copying the data line input, and copying whatever is feeding back into it from the previous output. A single SPDT relay serves as the multiplexer; by itself, however, it won't store anything, because you just end up with a loop of wire with no power source. So, we add a second latch relay into the feedback line which gives us a place to input power.

In its initial state, the circuit diagrammed on the left pulls the Q output low by tying to ground through two switch contacts and a diode. (It may be necessary to insert an additional resistor to ensure that any current that might be drawn via Q through the relay coil instead is not enough to cause it to trip.)

If the enable relay is energized, if D is low, the Q is also pulled low through the enable relay contact. If D is high, then Q is also pulled high, and in parallel the latch relay is energized, connecting a positive voltage supply; that supply current can't go anywhere, however, until the enable relay is de-energized, disconnecting the data line. When that happens, there is a short period of time while the contacts are switching during which the latch relay is disconnected from any power supply, which would could cause it to release, disconnecting the positive voltage supply and not storing anything. Thus, there is a capacitor across the coil terminals which needs to be large enough to keep the latch relay energized until the enable relay has finished switching. At that point, current flows from the positive voltage supply through two switch contacts, through the latch relay coil, through a diode, to ground, keeping the relay open, and keeping Q pulled high.

The next time the enable relay is activated, the path to the positive voltage supply is immediately broken, releasing the latch, and connecting Q to the data input again.

The diodes ensure that current cannot leak backwards to a low Q or D line through the relay coilds from a parallel memory cell attached to the same ground line.

Schematic diagram of a relay-based data latch.

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