On this Digilent/Xilinx Spartan 3e 1600 FPGA board, they use 270 ohm resistors as current limiting resistors.
In their guide they state:
The PS/2 port on the MicroBlaze Development Kit board is powered by 5V. Although the Spartan-3E FPGA is not a 5V-tolerant device, it can communicate with a 5V device using series current-limiting resistors, as shown in Figure 8-1.
I have seen level shifters and voltage dividers used, but I have not seen this.
Is this a valid design?
The design may be valid for this specific case and scenario, but it does not mean it's very good one and will work in all level shifting scenarios you come acroass.
First of all, as the FPGA IO is not 5V tolerant, the voltage must be limited to a level near the IO supply that does not cause damage. The IO pins are equipped with clamping diodes to protect from overvoltage and they are rated to handle some level of current safely.
So in this design, it appears that the designers chose 270 ohm series resistors, so that a 5V signal is clamped to safe voltage level by the internal protection diodes while the resistor limits the current to a safe level the diode can handle.
But in this instance, it must be noted, that this specific method is for a specific type of interface, it might not be suitable for all 5V signals.
First of all, the PS/2 interface is an oldschool open-drain interface with pull-up resistors to 5V and uses TTL voltage levels. The keyboard could have for example 2k pull-up resistors to 5V, and as the interface is bi-directional, either device or host can pull the wires low.
As TTL levels are used, both devices should consider voltages below 0.8V as low and voltages above 2.0V as high.
When the FPGA pulls low, it should output less than 0.4V but it may be sufficient if FPGA can pull below 0.8V, so 2k pull-ups on keyboard are weak enough for the FPGA to keyboard communications.
When the keyboard pulls low, the voltage is not affected by the FPGA or series resistor, so it will go as low as keyboard pulls it with internal pull-ups, it should be below 0.8V.
But when neither party pulls low, the voltage needs to only be above 2V, so even if the FPGA used 1.8V, the clamping diodes would keep the bus voltage above 2V, and current is further limited by the 2k pull-ups on keyboard and the 270 ohm resistors on FPGA pins. So curren required to clamp pin voltage is in the ballpark of 1 to 2 milliamps.
So while this is possible, usually the normal design procedure is to not rely on internal clamping diodes, but it may be a viable solution for a specific problem you need to solve if everything in the chip datasheet supports the decision.
A PS/2 device outputs its digital signal as 0V and 5V, in simple words sufficient for this answer.
The 0V level is OK for the 3.3V inputs and reads as low.
The 5V level could be too much for the 3.3V inputs, depending on the current driving capabilities of the PS/2 device, potentially damaging the FPGA. Therefore, the circuit inserts these series resistors.
The data sheet of the Spartan 3e tells us in table 73 "Absolute Maximum Ratings" on page 115 (excerpt):
| Symbol | Description | Conditions | Min | Max | Units |
|---|---|---|---|---|---|
| IIK | Input clamp current per I/O pin | –0.5 V < VIN < (VCCO + 0.5 V) | – | ± 100 | mA |
If the supply voltage of the FPGA is 3.3V, the resulting upper clamped voltage at the input pin is 3.3V + 0.5V = 3.8V.
If the PS/2 output voltage is 5V, the voltage difference over the resistor is 5V - 3.8V = 1.2V.
By Ohm's law this results in an input clamp current of 1.2V / 270Ω = 4.444mA.
This current is lower than the allowed maximum current. Therefore, these series resistors are "enough".
Note: This current is by far lower than the allowed maximum current. Therefore, we don't need to take tolerances into account.
A standard PS/2 port uses TTL logic levels so the 3.3V CMOS logic levels are legible to PS/2 device, and the PS2 logic low is unambiguous, just the logic high is potentially out of range.
The 270 ohm resistor limits the excess current that flows (into the protection diodes) when the PS/2 device asserts a logic high.
the attenuation caused by the series resistors is no enough to distort the logic signals beyond recognition.
I wanted to get this into the answers section. @rodo found the answer right on the Xilinx/AMD website. This was a great find that eliminates any speculation.
In article 19146:
https://adaptivesupport.amd.com/s/article/19146?language=en_US
The topic of the article is how to make the part 5v tolerant. In addition to describing how, they state the rationale behind it. In their process, they come up with a 263 ohm resistor. I suspect that the Digilent engineer(s) were aware of this article and then used a 270 ohm resistor.
