Questions tagged [eye-diagram]

Question 1

I am trying to understand eye diagrams and their significance in digital communications. I know that an eye diagram is typically used to visualize signal integrity, timing jitter, and noise in digital ...

Question 2

The plan is to communicate with multiple client MCUs (Node-B, Node-C,...) where each transmission is initiated by ONE master MCU (Node-A). The underlying PHY will be UART, but each RX AND TX line will ...

Question 3

I'm out of my area of expertise since I don't design digital stuff, but both the digital and test engineers are booked elsewhere yet big-boy scope available, it has fallen on me to test the LVDS eye ...

Question 4

While designing a board that uses PCIe gen5 interface, I was wondering how exactly gen5 standart achieves double data speed comparing to gen4 (32GT/s PCIe5 and 16GT/s PCIe4)? Both 4 and 5 are 16ghz ...

Question 5

Pre-emphasis is mainly used to boost high frequency component in the transmitted data. This is done by using FIR equalization. I am aware that, at the data transition, more current is pumped is pumped ...

Question 6

I was testing my display port diagram, all 4 lines. The first three look good, the 4th line looks like it has only one signal (not differential.) My question: Is the 4th line okey to be like this. (...

Question 7

There are some protocols with a dedicated line for clocking, and there are some protocols without a dedicated line for clocking. The last ones need a synchronization sequence which regularly zeroes ...

Question 8

I am reading articles about eye diagrams (for example, Anatomy of an Eye Diagram.) Everywhere in the description of the diagram formation method they talk about multiple overlay of patterns, about 001,...

Question 9

Used the SI Power Aware analysis on the DP/DM signals for this simulation: I'm having more issues on my Tx rather than the Rx. I do understand the Rx eye diagram but I'm struggling with the wild ...

Question 10

I have a SerDes communication that I am trying to perform the eye diagram to. I have an FPGA with generic IO's set up as LVDS SerDes and I will run them down to 300 MHz instead of my target frequency ...

Question 11

I am simulating eye diagram in ADS using the below setup The schematic is drawn following the ADS manual After simulating, I tried to plot the eye diagram using Density This is what I get but it is ...

Question 12

I measured the following waveform on a scope. It is a 100MBps Ethernet signal and I am measuring the TX+ and Tx- signals between the magnetics and RJ45 connector. I see what looks like a double ...

Question 13

When looking at the eye diagram as shown bellow, if we have high rise time which is cause by RC properties, what can we say about the impedance? What could cause bad rise time? Thanks.

Question 14

I got a new diff probe, I am trying it out on RS485. I'm triggering on the rising edge. The RS485 is running at 25Mhz. Does the eye diagram look good? Could I double the speed (50MHz) and be ok? (...

Question 15

I have created a differential channel and was testing the channel with simple testbench to check the eye diagram. Now I know the channel performance is very bad (It of several PCB transmission lines, ...

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Questions tagged [eye-diagram]

How can I draw an eye diagram by hand?

Help with Implementation of proprietary UART single-master and multi-client protocol

LVDS eye diagram

PCIe 4 and 5 GT/s characteristic, its connection to frequency [duplicate]

Effect of Pre-emphasis on Eye Diagram

Display port eye diagram evaluation

Why do we need an eye diagram?

How are patterns for eye diagrams sliced?

USB3.0 Differential Pair Eye Diagram - Transmitter Issues

Eye diagram testing setup

Issue with Eye Diagram in ADS

Measuring Ethernet Waveform on a scope

How to diagnose eye diagram slope on physical impedance problems?

RS485 Eye diagram - does it look good?

What does it mean if eye diagram voltage (0 and 1 level) goes negative?

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