Questions tagged [microsemi-fpga]

Question 1

I have a Microchip / Microsemi PolarFire FPGA design built in Libero where I instantiate a RISC-V core (System Builder) and three additional PF_RAMS (PolarFire SRAM) IP blocks that I want to ...

Question 2

I'm trying to simulate Core1553BRT_APB LiberoSoc IP Core via user testbench provided by this Core. When I launch RTL simulation (I'm using ModelSim Microsemi Pro 2020.4), it gives me Error (...

Question 3

I am implementing a Manchester decoder for a serial input with rate 10mbps +/- 0.01% bit timing error. The sampling frequency is 160MHz +/- 50ppm. Longest packet is 1526 bytes * 8 = 12208 bits. So ...

Question 4

I am trying to implement a fixed delay line using carry chain inside FPGA (Microchip's IGLOO2). Currently one of the constraints in this project is to use carry chain as delay elements (not any other ...

Question 5

I have designed a simple internal SRAM memory where I initiate the write enable and read enable via DIP switches. Verilog input wire has been declared in the simple memory read write which connects to ...

Question 6

I currently work with two FPGAs, Microchip/Microsemi ProASIC3E and AMD/Xilinx Zynq-7020. In their datasheets, the recommended minimum operating frequency is 1.5 MHz for the A3PE ProASIC3E chip. The ...

Question 7

We are using the FPGA ProASIC3E A3PE1500-PQ208. The FPGA got internally short circuited during runtime. The FPGA IO Supply Voltage and FPGA ground are permanently short circuited and it is not ...

Question 8

Some of the labels used in back-annotated netlist descriptions generated by Microchip (Microsemi) Libero rely on forward slash naming conventions as shown below ...

Question 9

I have a test bench where I'm using a SystemVerilog bind construct. My test bench follows a similar organization to the one described at this link Every time I run it, error vsim-3171 shows up. I came ...

Question 10

I am using a ProASIC3E PQ208 FPGA and Libero tool to write the vhdl code and program the board on which the FPGA is soldered. When I try to open Libero again to program file, it starts the synthesis ...

Question 11

I have been using Xilinx FPGA devices for a while and I use HLS extensively to create parts of my design. I have currently switched to Actel FPGA devices and specifically the ProASIC3 family, and ...

Question 12

I am woking with Microsemi Polarfire Splashkit evaluation board (Microchip's Polarfire MPF300T FPGA on board). My project has Mi-V RV32 Softcore processor (RISC-V ISA) and I am writing firmware for it....

Question 13

I instantiated a crystal oscillator (and CCC) in a Microchip/Microsemi IGLOO2 FPGA design, and the oscillator's VHDL module has a XTL input pin. What is the proper preparation/wiring for simulation? ...

Question 14

An interconnect connects one or more masters to one or more slaves in a sort of system on chip design. In such a scenario there would be a master containing a standard bus like Avalon-MM, AMBA AXI, ...

Question 15

In FPGA projects, the files are usually named after the entity they contain. I am trying to figure out these things: Is it a good practice to have multiple entities in same file? What if entity and ...

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Questions tagged [microsemi-fpga]

PolarFire PF_RAMS memory init fails: “sNVM page insufficient” when initializing 3 SRAM IPs — how to force init into LUT/BRAM instead of sNVM?

Error (suppressible): (vsim-3584) Module parameter 'ARGVALUE0' not found for override

signal rate error handling in FPGA

Delay line using carry chain in IGLOO2 FPGA

Giving write enable signal externally by DIP switch to FPGA memory

Minimum FPGA clock frequency

Microchip FPGA Internal Short Circuit

Problem with back annotated netlist signals naming for simulation purposes in Modelsim

Error message vsim-3171 keeps popping up in Modelsim DE 2021.1 even though it was solved in Modelsim ME 10.2c

Libero does synthesis again before programming the device

HLS like programming on Actel devices

Why program for MI-V bigger than 64 kB does not build properly?

FPGA simulation with crystal oscillator what to do with XTL input?

Is it possible to write an "interconnect" in VHDL by hand?

Is there a reason to have different files or entities with same name in FPGA project?

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