The problem I'm facing is closely related to this: https://electronics.stackexchange.com/a/540545/238188 . I found I could not simulate a T Flip-Flop without a reset on Multisim Live.

I found that I could not get a T Flip-Flop without a reset to simulate in SystemVerilog either, but I could get a JK Flip-Flop without a reset to simulate. This is because I can set a JK Flip-Flop to a known state using J = 0, K = 1 or K = 1, J = 0.

The design code:
``` 
module t_ff(input logic t, clk, output logic q, q_bar);
 parameter HOLD = 1'b0,
 TOGGLE = 1'b1;
 
 always_ff @(posedge clk)
 case (t)
 HOLD: q <= q;
 TOGGLE: q <= ~q;
 default: q <= 1'bz;
 endcase
 
 assign q_bar = ~q;
endmodule

```
I tried using `bit` in the testbench, but that did not work either (just as I expected). I understand that a reset is important for a Flip-Flop in IC Design, but can't we build a Flip-Flop without a reset? I think the T Flip-Flop can be used without a reset in applications when the input for the flip-flop comes from another digital circuit. 

I also came across this question and answer:
https://electronics.stackexchange.com/q/433825/238188

But that answer does not mention what should be done if we don't use a reset.

My question arises from this conversation I had with user "Elliot Alderson"
> @ElliotAlderson if you design a T Flip-Flop where the only inputs are T and the clock, then there is no way to set the output to a known state in simulation that supports 'X'. Further reading: sutherland-hdl.com/papers/… – Shashank V M Jan 3 at 16:32 

> @ShashankVM I think you can, with an initial block in Verilog for example. Sutherland writes very useful papers...did you read the first sentence of the second paragraph in Section 7? – Elliot Alderson Jan 3 at 17:42 (https://electronics.stackexchange.com/questions/540518/why-cant-i-make-flip-flops-in-logic-simulators/540545#comment1401517_540523)

"Elliot Alderson" says we can use an initial block to set the output to a known state. I followed that comment and read the section of that paper by Sutherland. I found it seems possible according to the paper, but how is it done? 

Link to the paper: https://sutherland-hdl.com/papers/2013-DVCon_In-love-with-my-X_paper.pdf

How is this problem handled in **Gate-level simulations**?