Disclaimer: I am not sure if this is the right place to ask this.

I am trying to create an sdram controller for the numato [mimas v2][1] fpga. The board contains an LPDDR module (either the [Micron MT46H32M16LF][2] or the [Winbond W949D6CBHX6E][3], which operates the same way). The clock is transmitted using the differential pair ck, ck_n. In the constraints file for my design, the signals are defined as DIFF_MOBILE_DDR (while most other signals are defined as MOBILE_DDR: they don't seem to cause troubles).

My first try was to set ck to the clock, and ck_n to not(clock). However, I get the following error message in Xilinx ISE:

> The I/O component "ck" has an illegal IOSTANDARD value. The
 IOB component is configured to use single-ended signaling and can not use
 differential IOSTANDARD value DIFF_MOBILE_DDR. Two ways to rectify this
 issue are: 1) Change the IOSTANDARD value to a single-ended standard. 2)
 Correct the I/O connectivity by instantiating a differential I/O buffer.

(and a similar message for ck_n)

My guess is that I have to use a differential I/O buffer. How can I do this is Xilinx ISE?

Googling didn't lead to much. [A related question][4] which seems to suggest that there is some HDL from a library that does what I want, but I still have no idea which one.


 [1]: http://numato.com/mimas-v2-spartan-6-fpga-development-board-with-ddr-sdram/
 [2]: https://www.google.cz/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&uact=8&ved=0ahUKEwiplfLh0ZTOAhWEVhQKHa49DagQFgguMAE&url=http%3A%2F%2Fwww.alldatasheet.com%2Fdatasheet-pdf%2Fpdf%2F105844%2FMICRON%2FMT46H32M16LF.html&usg=AFQjCNGgcoD-4SS9g7RpJrxJfdTwKS8y2w
 [3]: http://pdf1.alldatasheet.com/datasheet-pdf/view/443847/WINBOND/W949D6CBHX6E/+3__859VThMwPPh+b.ChLGMMTkKT+/datasheet.pdf
 [4]: https://forums.xilinx.com/t5/Synthesis/Differential-buffer-insertion-in-XST-or-VHDL/td-p/460932