User Simon Richter

10 votes

2 answers

2k views

Bypass capacitors between via and chip?

asked Jul 31, 2014 at 8:52

6 votes

3 answers

1k views

Smaller footprint for SMD capacitors

asked Jul 7, 2014 at 21:44

6 votes

2 answers

1k views

Size of SMD pads for components with high tolerances

asked Jul 27, 2014 at 23:25

5 votes

2 answers

2k views

Multiple traces for single connection in Eagle

asked Jul 3, 2014 at 14:47

4 votes

2 answers

320 views

Breakout for TLA-QFN with exposed pad

asked Aug 24, 2016 at 23:20

4 votes

1 answer

3k views

Schematic layout for inline and pull-up/down resistors

asked Nov 23, 2016 at 13:29

4 votes

3 answers

5k views

Protecting against a SSR failing closed

asked Jan 18, 2019 at 3:48

3 votes

1 answer

2k views

Isolated voltage and current measurement

asked Sep 2, 2016 at 16:30

3 votes

1 answer

2k views

1.2V, 2.5V and 3.3V from 5V

asked May 20, 2014 at 16:39

3 votes

2 answers

865 views

Bypass capacitor placement in Eagle

asked May 23, 2014 at 10:56

3 votes

3 answers

1k views

Verifying Cat5e cabling

asked Feb 22, 2011 at 17:44

3 votes

1 answer

546 views

Understanding the second transformer in PoE designs

asked Dec 23, 2015 at 3:30

3 votes

0 answers

84 views

Synchronizing SCPI communication over RS232

asked Oct 31, 2023 at 9:00

2 votes

1 answer

3k views

Protecting I2C bus with diodes

asked May 15, 2015 at 1:43

2 votes

1 answer

247 views

CycloneIV PCIe hard IP fixedclk_serdes generation

asked Oct 15, 2015 at 12:44

2 votes

1 answer

190 views

Eagle: Pins on FPGA exchangeable, depending on configuration

asked May 17, 2014 at 16:23

2 votes

1 answer

299 views

DDR3 DQS "preamble"

asked Sep 11, 2021 at 13:51

1 vote

2 answers

127 views

Detecting stuck logic in testbench

asked Apr 17, 2023 at 10:30

1 vote

0 answers

102 views

Stability of MRAM values after power loss during write

asked Jun 13, 2023 at 4:37

1 vote

0 answers

108 views

MII/GMII switch for 10/100 Mbps vs 1Gbps

asked Dec 29, 2020 at 18:57

1 vote

0 answers

44 views

Avoiding node removal during optimization for preliminary estimation

asked May 2, 2021 at 15:00

1 vote

3 answers

325 views

Modeling bidirectional propagation delays

asked Jul 30, 2021 at 11:06

1 vote

0 answers

106 views

BGA escape routing, understanding Altera app note

asked Sep 3, 2016 at 21:40

1 vote

1 answer

264 views

Baking 0603 Components

asked Jul 29, 2016 at 17:14

1 vote

0 answers

134 views

Eagle: IC package variant, different pins bonded out

asked May 17, 2014 at 17:57

1 vote

2 answers

383 views

Distributing 700W at 5V over 10m

asked May 12, 2014 at 8:44

1 vote

1 answer

557 views

Ground Plane, Bypass Capacitors and Differential Pairs

asked Jul 15, 2014 at 20:13

1 vote

0 answers

430 views

Improving PCB layout for regulator circuit

asked Nov 14, 2014 at 12:47

1 vote

0 answers

40 views

Can I combine AS and JTAG headers for CycloneIV?

asked Jan 2 at 4:17

1 vote

1 answer

420 views

SDC constraints for reusable component

asked Oct 14, 2018 at 21:34

Stack Exchange Network

39 Questions

Bypass capacitors between via and chip?

Smaller footprint for SMD capacitors

Size of SMD pads for components with high tolerances

Multiple traces for single connection in Eagle

Breakout for TLA-QFN with exposed pad

Schematic layout for inline and pull-up/down resistors

Protecting against a SSR failing closed

Isolated voltage and current measurement

1.2V, 2.5V and 3.3V from 5V

Bypass capacitor placement in Eagle

Verifying Cat5e cabling

Understanding the second transformer in PoE designs

Synchronizing SCPI communication over RS232

Protecting I2C bus with diodes

CycloneIV PCIe hard IP fixedclk_serdes generation

Eagle: Pins on FPGA exchangeable, depending on configuration

DDR3 DQS "preamble"

Detecting stuck logic in testbench

Stability of MRAM values after power loss during write

MII/GMII switch for 10/100 Mbps vs 1Gbps

Avoiding node removal during optimization for preliminary estimation

Modeling bidirectional propagation delays

BGA escape routing, understanding Altera app note

Baking 0603 Components

Eagle: IC package variant, different pins bonded out

Distributing 700W at 5V over 10m

Ground Plane, Bypass Capacitors and Differential Pairs

Improving PCB layout for regulator circuit

Can I combine AS and JTAG headers for CycloneIV?

SDC constraints for reusable component