[AMDGPU] Avoid undefs in hazard-gfx1250-flat-scr-hi.mir. NFC

[rampitec]

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[rampitec]

• [AMDGPU] Avoid undefs in hazard-gfx1250-flat-scr-hi.mir. NFC #170396 👈
• [AMDGPU] Handle phys regs in flat_scratch_base_hi operand check #170395
• main

This stack of pull requests is managed by sgh.

[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Stanislav Mekhanoshin (rampitec)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/170396.diff

1 Files Affected:

• (modified) llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir (+54-30)

diff --git a/llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir b/llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir index e3b28c5518695..5dafa1b72ed10 100644 --- a/llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir +++ b/llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir @@ -8,10 +8,12 @@ body: | bb.0: ; GCN-LABEL: name: s_ashr_i64 - ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi - ; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 undef %2:sreg_64, [[COPY]], implicit-def $scc + ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF + ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi + ; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[DEF]], [[COPY]], implicit-def $scc + %1:sreg_64 = IMPLICIT_DEF %0:sreg_32 = COPY $src_flat_scratch_base_hi - %2:sreg_64 = S_ASHR_I64 undef %1:sreg_64, %0, implicit-def $scc + %2:sreg_64 = S_ASHR_I64 %1:sreg_64, %0, implicit-def $scc ... --- @@ -21,10 +23,12 @@ body: | bb.0: ; GCN-LABEL: name: s_lshl_b64 - ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi - ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 undef %2:sreg_64, [[COPY]], implicit-def $scc + ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF + ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi + ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[DEF]], [[COPY]], implicit-def $scc + %1:sreg_64 = IMPLICIT_DEF %0:sreg_32 = COPY $src_flat_scratch_base_hi - %2:sreg_64 = S_LSHL_B64 undef %1:sreg_64, %0, implicit-def $scc + %2:sreg_64 = S_LSHL_B64 %1:sreg_64, %0, implicit-def $scc ... --- @@ -34,10 +38,12 @@ body: | bb.0: ; GCN-LABEL: name: s_lshr_b64 - ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi - ; GCN-NEXT: [[S_LSHR_B64_:%[0-9]+]]:sreg_64 = S_LSHR_B64 undef %2:sreg_64, [[COPY]], implicit-def $scc + ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF + ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi + ; GCN-NEXT: [[S_LSHR_B64_:%[0-9]+]]:sreg_64 = S_LSHR_B64 [[DEF]], [[COPY]], implicit-def $scc + %1:sreg_64 = IMPLICIT_DEF %0:sreg_32 = COPY $src_flat_scratch_base_hi - %2:sreg_64 = S_LSHR_B64 undef %1:sreg_64, %0, implicit-def $scc + %2:sreg_64 = S_LSHR_B64 %1:sreg_64, %0, implicit-def $scc ... --- @@ -47,10 +53,12 @@ body: | bb.0: ; GCN-LABEL: name: s_bfe_i64 - ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi - ; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 undef %2:sreg_64, [[COPY]], implicit-def $scc + ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF + ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi + ; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[DEF]], [[COPY]], implicit-def $scc + %1:sreg_64 = IMPLICIT_DEF %0:sreg_32 = COPY $src_flat_scratch_base_hi - %2:sreg_64 = S_BFE_I64 undef %1:sreg_64, %0, implicit-def $scc + %2:sreg_64 = S_BFE_I64 %1:sreg_64, %0, implicit-def $scc ... --- @@ -60,10 +68,12 @@ body: | bb.0: ; GCN-LABEL: name: s_bfe_u64 - ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi - ; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 undef %2:sreg_64, [[COPY]], implicit-def $scc + ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF + ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi + ; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[DEF]], [[COPY]], implicit-def $scc + %1:sreg_64 = IMPLICIT_DEF %0:sreg_32 = COPY $src_flat_scratch_base_hi - %2:sreg_64 = S_BFE_U64 undef %1:sreg_64, %0, implicit-def $scc + %2:sreg_64 = S_BFE_U64 %1:sreg_64, %0, implicit-def $scc ... --- @@ -86,10 +96,14 @@ body: | bb.0: ; GCN-LABEL: name: s_bitcmp0_b64 - ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi - ; GCN-NEXT: S_BITCMP0_B64 undef %1:sreg_64, [[COPY]], implicit undef $scc, implicit-def $scc + ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF + ; GCN-NEXT: $scc = IMPLICIT_DEF + ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi + ; GCN-NEXT: S_BITCMP0_B64 [[DEF]], [[COPY]], implicit $scc, implicit-def $scc + %1:sreg_64 = IMPLICIT_DEF + $scc = IMPLICIT_DEF %0:sreg_32 = COPY $src_flat_scratch_base_hi - S_BITCMP0_B64 undef %1:sreg_64, %0, implicit undef $scc, implicit-def $scc + S_BITCMP0_B64 %1:sreg_64, %0, implicit $scc, implicit-def $scc ... --- @@ -99,10 +113,14 @@ body: | bb.0: ; GCN-LABEL: name: s_bitcmp1_b64 - ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi - ; GCN-NEXT: S_BITCMP1_B64 undef %1:sreg_64, [[COPY]], implicit undef $scc, implicit-def $scc + ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF + ; GCN-NEXT: $scc = IMPLICIT_DEF + ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi + ; GCN-NEXT: S_BITCMP1_B64 [[DEF]], [[COPY]], implicit $scc, implicit-def $scc + %1:sreg_64 = IMPLICIT_DEF + $scc = IMPLICIT_DEF %0:sreg_32 = COPY $src_flat_scratch_base_hi - S_BITCMP1_B64 undef %1:sreg_64, %0, implicit undef $scc, implicit-def $scc + S_BITCMP1_B64 %1:sreg_64, %0, implicit $scc, implicit-def $scc ... --- @@ -125,10 +143,12 @@ body: | bb.0: ; GCN-LABEL: name: s_bitset0_b64 - ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi - ; GCN-NEXT: [[S_BITSET0_B64_:%[0-9]+]]:sreg_64 = S_BITSET0_B64 [[COPY]], undef [[S_BITSET0_B64_]], implicit-def $scc + ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF + ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi + ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_64 = S_BITSET0_B64 [[COPY]], [[DEF]], implicit-def $scc + %1:sreg_64 = IMPLICIT_DEF %0:sreg_32 = COPY $src_flat_scratch_base_hi - %1:sreg_64 = S_BITSET0_B64 %0, undef %1:sreg_64, implicit-def $scc + %1:sreg_64 = S_BITSET0_B64 %0, %1:sreg_64, implicit-def $scc ... --- @@ -138,10 +158,12 @@ body: | bb.0: ; GCN-LABEL: name: s_bitset1_b64 - ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi - ; GCN-NEXT: [[S_BITSET1_B64_:%[0-9]+]]:sreg_64 = S_BITSET1_B64 [[COPY]], undef [[S_BITSET1_B64_]], implicit-def $scc + ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF + ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi + ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_64 = S_BITSET1_B64 [[COPY]], [[DEF]], implicit-def $scc + %1:sreg_64 = IMPLICIT_DEF %0:sreg_32 = COPY $src_flat_scratch_base_hi - %1:sreg_64 = S_BITSET1_B64 %0, undef %1:sreg_64, implicit-def $scc + %1:sreg_64 = S_BITSET1_B64 %0, %1:sreg_64, implicit-def $scc ... --- @@ -151,8 +173,10 @@ body: | bb.0: ; GCN-LABEL: name: s_ashr_i64_phys_dst - ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi - ; GCN-NEXT: $sgpr0_sgpr1 = S_ASHR_I64 undef %1:sreg_64, [[COPY]], implicit-def $scc + ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF + ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi + ; GCN-NEXT: $sgpr0_sgpr1 = S_ASHR_I64 [[DEF]], [[COPY]], implicit-def $scc + %1:sreg_64 = IMPLICIT_DEF %0:sreg_32 = COPY $src_flat_scratch_base_hi - $sgpr0_sgpr1 = S_ASHR_I64 undef %1:sreg_64, %0, implicit-def $scc + $sgpr0_sgpr1 = S_ASHR_I64 %1:sreg_64, %0, implicit-def $scc ...