Revert "[InlineAsm] wrap ConstraintCode in enum class NFC (llvm#66003)"

This reverts commit 2ca4d13. Also revert the followup, "[InlineAsm] fix botched merge conflict resolution" This reverts commit 8b9bf3a. There were SystemZ and Mips build errors, too many to fix forward.

Author: rnk

llvm/include/llvm/CodeGen/SelectionDAGISel.h

@@ -89,10 +89,9 @@ class SelectionDAGISel : public MachineFunctionPass {
  /// not match or is not implemented, return true. The resultant operands
  /// (which will appear in the machine instruction) should be added to the
  /// OutOps vector.
- virtual bool
- SelectInlineAsmMemoryOperand(const SDValue &Op,
- InlineAsm::ConstraintCode ConstraintID,
- std::vector<SDValue> &OutOps) {
+ virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ unsigned ConstraintID,
+ std::vector<SDValue> &OutOps) {
  return true;
  }
 

llvm/include/llvm/CodeGen/TargetLowering.h

@@ -4833,17 +4833,16 @@ class TargetLowering : public TargetLoweringBase {
  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
  StringRef Constraint, MVT VT) const;
 
- virtual InlineAsm::ConstraintCode
- getInlineAsmMemConstraint(StringRef ConstraintCode) const {
+ virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
  if (ConstraintCode == "m")
- return InlineAsm::ConstraintCode::m;
+ return InlineAsm::Constraint_m;
  if (ConstraintCode == "o")
- return InlineAsm::ConstraintCode::o;
+ return InlineAsm::Constraint_o;
  if (ConstraintCode == "X")
- return InlineAsm::ConstraintCode::X;
+ return InlineAsm::Constraint_X;
  if (ConstraintCode == "p")
- return InlineAsm::ConstraintCode::p;
- return InlineAsm::ConstraintCode::Unknown;
+ return InlineAsm::Constraint_p;
+ return InlineAsm::Constraint_Unknown;
  }
 
  /// Try to replace an X constraint, which matches anything, with another that

llvm/include/llvm/IR/InlineAsm.h

@@ -217,6 +217,48 @@ class InlineAsm final : public Value {
  Extra_MayLoad = 8,
  Extra_MayStore = 16,
  Extra_IsConvergent = 32,
+
+ // Memory constraint codes.
+ // These could be tablegenerated but there's little need to do that since
+ // there's plenty of space in the encoding to support the union of all
+ // constraint codes for all targets.
+ // Addresses are included here as they need to be treated the same by the
+ // backend, the only difference is that they are not used to actaully
+ // access memory by the instruction.
+ // TODO: convert to enum?
+ Constraint_Unknown = 0,
+ Constraint_es,
+ Constraint_i,
+ Constraint_k,
+ Constraint_m,
+ Constraint_o,
+ Constraint_v,
+ Constraint_A,
+ Constraint_Q,
+ Constraint_R,
+ Constraint_S,
+ Constraint_T,
+ Constraint_Um,
+ Constraint_Un,
+ Constraint_Uq,
+ Constraint_Us,
+ Constraint_Ut,
+ Constraint_Uv,
+ Constraint_Uy,
+ Constraint_X,
+ Constraint_Z,
+ Constraint_ZB,
+ Constraint_ZC,
+ Constraint_Zy,
+
+ // Address constraints
+ Constraint_p,
+ Constraint_ZQ,
+ Constraint_ZR,
+ Constraint_ZS,
+ Constraint_ZT,
+
+ Constraints_Max = Constraint_ZT,
  };
 
  // Inline asm operands map to multiple SDNode / MachineInstr operands.
@@ -232,46 +274,6 @@ class InlineAsm final : public Value {
  Func = 7, // Address operand of function call
  };
 
- // Memory constraint codes.
- // Addresses are included here as they need to be treated the same by the
- // backend, the only difference is that they are not used to actaully
- // access memory by the instruction.
- enum class ConstraintCode : uint32_t {
- Unknown = 0,
- es,
- i,
- k,
- m,
- o,
- v,
- A,
- Q,
- R,
- S,
- T,
- Um,
- Un,
- Uq,
- Us,
- Ut,
- Uv,
- Uy,
- X,
- Z,
- ZB,
- ZC,
- Zy,
-
- // Address constraints
- p,
- ZQ,
- ZR,
- ZS,
- ZT,
-
- Max = ZT,
- };
-
  // These are helper methods for dealing with flags in the INLINEASM SDNode
  // in the backend.
  //
@@ -373,14 +375,11 @@ class InlineAsm final : public Value {
  return true;
  }
 
- ConstraintCode getMemoryConstraintID() const {
+ // TODO: convert to enum?
+ unsigned getMemoryConstraintID() const {
  assert((isMemKind() || isFuncKind()) &&
  "Not expected mem or function flag!");
- uint32_t D = getData();
- assert(D < static_cast<uint32_t>(ConstraintCode::Max) &&
- D >= static_cast<uint32_t>(ConstraintCode::Unknown) &&
- "unexpected value for memory constraint");
- return static_cast<ConstraintCode>(D);
+ return getData();
  }
 
  /// setMatchingOp - Augment an existing flag with information indicating
@@ -404,11 +403,12 @@ class InlineAsm final : public Value {
 
  /// setMemConstraint - Augment an existing flag with the constraint code for
  /// a memory constraint.
- void setMemConstraint(ConstraintCode C) {
+ void setMemConstraint(unsigned Constraint) {
  assert((isMemKind() || isFuncKind()) &&
  "Flag is not a memory or function constraint!");
+ assert(Constraint <= Constraints_Max && "Unknown constraint ID");
  assert(getData() == 0 && "Mem constraint already set");
- setData(static_cast<uint32_t>(C));
+ setData(Constraint);
  }
  /// clearMemConstraint - Similar to setMemConstraint(0), but without the
  /// assertion checking that the constraint has not been set previously.
@@ -443,63 +443,63 @@ class InlineAsm final : public Value {
  return Result;
  }
 
- static StringRef getMemConstraintName(ConstraintCode C) {
- switch (C) {
- case ConstraintCode::es:
+ static StringRef getMemConstraintName(unsigned Constraint) {
+ switch (Constraint) {
+ case InlineAsm::Constraint_es:
  return "es";
- case ConstraintCode::i:
+ case InlineAsm::Constraint_i:
  return "i";
- case ConstraintCode::k:
+ case InlineAsm::Constraint_k:
  return "k";
- case ConstraintCode::m:
+ case InlineAsm::Constraint_m:
  return "m";
- case ConstraintCode::o:
+ case InlineAsm::Constraint_o:
  return "o";
- case ConstraintCode::v:
+ case InlineAsm::Constraint_v:
  return "v";
- case ConstraintCode::A:
+ case InlineAsm::Constraint_A:
  return "A";
- case ConstraintCode::Q:
+ case InlineAsm::Constraint_Q:
  return "Q";
- case ConstraintCode::R:
+ case InlineAsm::Constraint_R:
  return "R";
- case ConstraintCode::S:
+ case InlineAsm::Constraint_S:
  return "S";
- case ConstraintCode::T:
+ case InlineAsm::Constraint_T:
  return "T";
- case ConstraintCode::Um:
+ case InlineAsm::Constraint_Um:
  return "Um";
- case ConstraintCode::Un:
+ case InlineAsm::Constraint_Un:
  return "Un";
- case ConstraintCode::Uq:
+ case InlineAsm::Constraint_Uq:
  return "Uq";
- case ConstraintCode::Us:
+ case InlineAsm::Constraint_Us:
  return "Us";
- case ConstraintCode::Ut:
+ case InlineAsm::Constraint_Ut:
  return "Ut";
- case ConstraintCode::Uv:
+ case InlineAsm::Constraint_Uv:
  return "Uv";
- case ConstraintCode::Uy:
+ case InlineAsm::Constraint_Uy:
  return "Uy";
- case ConstraintCode::X:
+ case InlineAsm::Constraint_X:
  return "X";
- case ConstraintCode::Z:
+ case InlineAsm::Constraint_Z:
  return "Z";
- case ConstraintCode::ZB:
+ case InlineAsm::Constraint_ZB:
  return "ZB";
- case ConstraintCode::ZC:
+ case InlineAsm::Constraint_ZC:
  return "ZC";
- case ConstraintCode::Zy:
+ case InlineAsm::Constraint_Zy:
  return "Zy";
- case ConstraintCode::p:
+ case InlineAsm::Constraint_p:
  return "p";
- case ConstraintCode::ZQ:
+ case InlineAsm::Constraint_ZQ:
  return "ZQ";
- case ConstraintCode::ZR:
+ case InlineAsm::Constraint_ZR:
  return "ZR";
- case ConstraintCode::ZS:
+ case InlineAsm::Constraint_ZS:
  return "ZS";
- case ConstraintCode::ZT:
+ case InlineAsm::Constraint_ZT:
  return "ZT";
  default:
  llvm_unreachable("Unknown memory constraint");

llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp

@@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm(
  switch (OpInfo.Type) {
  case InlineAsm::isOutput:
  if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- const InlineAsm::ConstraintCode ConstraintID =
+ unsigned ConstraintID =
  TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
+ assert(ConstraintID != InlineAsm::Constraint_Unknown &&
  "Failed to convert memory constraint code to constraint id.");
 
  // Add information to the INLINEASM instruction to know about this
@@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm(
 
  assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
 
- const InlineAsm::ConstraintCode ConstraintID =
+ unsigned ConstraintID =
  TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
  InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
  OpFlags.setMemConstraint(ConstraintID);

llvm/lib/CodeGen/MachineInstr.cpp

@@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
  }
 
  if (F.isMemKind()) {
- const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
+ const unsigned MCID = F.getMemoryConstraintID();
  OS << ":" << InlineAsm::getMemConstraintName(MCID);
  }
 

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

@@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
  switch (OpInfo.Type) {
  case InlineAsm::isOutput:
  if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- const InlineAsm::ConstraintCode ConstraintID =
+ unsigned ConstraintID =
  TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
+ assert(ConstraintID != InlineAsm::Constraint_Unknown &&
  "Failed to convert memory constraint code to constraint id.");
 
  // Add information to the INLINEASM node to know about this output.
@@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
  TLI.getPointerTy(DAG.getDataLayout()) &&
  "Memory operands expect pointer values");
 
- const InlineAsm::ConstraintCode ConstraintID =
+ unsigned ConstraintID =
  TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
+ assert(ConstraintID != InlineAsm::Constraint_Unknown &&
  "Failed to convert memory constraint code to constraint id.");
 
  // Add information to the INLINEASM node to know about this input.
@@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
  }
 
  if (OpInfo.ConstraintType == TargetLowering::C_Address) {
- const InlineAsm::ConstraintCode ConstraintID =
+ unsigned ConstraintID =
  TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
+ assert(ConstraintID != InlineAsm::Constraint_Unknown &&
  "Failed to convert memory constraint code to constraint id.");
 
  InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);

llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

@@ -2101,8 +2101,7 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
 
  // Otherwise, this is a memory operand. Ask the target to select it.
  std::vector<SDValue> SelOps;
- const InlineAsm::ConstraintCode ConstraintID =
- Flags.getMemoryConstraintID();
+ unsigned ConstraintID = Flags.getMemoryConstraintID();
  if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
  report_fatal_error("Could not match memory address. Inline asm"
  " failure!");

llvm/lib/CodeGen/TargetInstrInfo.cpp

@@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment(
  }
 
  if (F.isMemKind()) {
- InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
+ const unsigned MCID = F.getMemoryConstraintID();
  OS << ":" << InlineAsm::getMemConstraintName(MCID);
  }
 

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

@@ -62,7 +62,7 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
  /// inline asm expressions.
  bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- InlineAsm::ConstraintCode ConstraintID,
+ unsigned ConstraintID,
  std::vector<SDValue> &OutOps) override;
 
  template <signed Low, signed High, signed Scale>
@@ -533,14 +533,13 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) {
 #endif
 
 bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
- std::vector<SDValue> &OutOps) {
+ const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
  switch(ConstraintID) {
  default:
  llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::ConstraintCode::m:
- case InlineAsm::ConstraintCode::o:
- case InlineAsm::ConstraintCode::Q:
+ case InlineAsm::Constraint_m:
+ case InlineAsm::Constraint_o:
+ case InlineAsm::Constraint_Q:
  // We need to make sure that this one operand does not end up in XZR, thus
  // require the address to be in a PointerRegClass register.
  const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();

llvm/lib/Target/AArch64/AArch64ISelLowering.h

@@ -1169,10 +1169,9 @@ class AArch64TargetLowering : public TargetLowering {
  std::vector<SDValue> &Ops,
  SelectionDAG &DAG) const override;
 
- InlineAsm::ConstraintCode
- getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+ unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
  if (ConstraintCode == "Q")
- return InlineAsm::ConstraintCode::Q;
+ return InlineAsm::Constraint_Q;
  // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
  // followed by llvm_unreachable so we'll leave them unimplemented in
  // the backend for now.