[NFC] Correct typo: invertion -> inversion (llvm#147995)

Author: frasercrmck

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

@@ -9272,7 +9272,7 @@ LegalizerHelper::lowerISFPCLASS(MachineInstr &MI) {
  APInt AllOneMantissa = APFloat::getLargest(Semantics).bitcastToAPInt() & ~Inf;
  APInt QNaNBitMask =
  APInt::getOneBitSet(BitSize, AllOneMantissa.getActiveBits() - 1);
- APInt InvertionMask = APInt::getAllOnes(DstTy.getScalarSizeInBits());
+ APInt InversionMask = APInt::getAllOnes(DstTy.getScalarSizeInBits());
 
  auto SignBitC = MIRBuilder.buildConstant(IntTy, SignBit);
  auto ValueMaskC = MIRBuilder.buildConstant(IntTy, ValueMask);
@@ -9400,7 +9400,7 @@ LegalizerHelper::lowerISFPCLASS(MachineInstr &MI) {
  NormalRes = MIRBuilder.buildAnd(DstTy, NormalRes, Sign);
  else if (PartialCheck == fcPosNormal) {
  auto PosSign = MIRBuilder.buildXor(
- DstTy, Sign, MIRBuilder.buildConstant(DstTy, InvertionMask));
+ DstTy, Sign, MIRBuilder.buildConstant(DstTy, InversionMask));
  NormalRes = MIRBuilder.buildAnd(DstTy, NormalRes, PosSign);
  }
  appendToRes(NormalRes);

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -9054,14 +9054,14 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
  APInt AllOneMantissa = APFloat::getLargest(Semantics).bitcastToAPInt() & ~Inf;
  APInt QNaNBitMask =
  APInt::getOneBitSet(BitSize, AllOneMantissa.getActiveBits() - 1);
- APInt InvertionMask = APInt::getAllOnes(ResultVT.getScalarSizeInBits());
+ APInt InversionMask = APInt::getAllOnes(ResultVT.getScalarSizeInBits());
 
  SDValue ValueMaskV = DAG.getConstant(ValueMask, DL, IntVT);
  SDValue SignBitV = DAG.getConstant(SignBit, DL, IntVT);
  SDValue ExpMaskV = DAG.getConstant(ExpMask, DL, IntVT);
  SDValue ZeroV = DAG.getConstant(0, DL, IntVT);
  SDValue InfV = DAG.getConstant(Inf, DL, IntVT);
- SDValue ResultInvertionMask = DAG.getConstant(InvertionMask, DL, ResultVT);
+ SDValue ResultInversionMask = DAG.getConstant(InversionMask, DL, ResultVT);
 
  SDValue Res;
  const auto appendResult = [&](SDValue PartialRes) {
@@ -9205,7 +9205,7 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
  PartialRes = DAG.getNode(ISD::AND, DL, ResultVT, PartialRes, SignV);
  else if (PartialCheck == fcPosNormal) {
  SDValue PosSignV =
- DAG.getNode(ISD::XOR, DL, ResultVT, SignV, ResultInvertionMask);
+ DAG.getNode(ISD::XOR, DL, ResultVT, SignV, ResultInversionMask);
  PartialRes = DAG.getNode(ISD::AND, DL, ResultVT, PartialRes, PosSignV);
  }
  if (IsF80)
@@ -9217,7 +9217,7 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
  if (!Res)
  return DAG.getConstant(IsInverted, DL, ResultVT);
  if (IsInverted)
- Res = DAG.getNode(ISD::XOR, DL, ResultVT, Res, ResultInvertionMask);
+ Res = DAG.getNode(ISD::XOR, DL, ResultVT, Res, ResultInversionMask);
  return Res;
 }
 

llvm/lib/Target/NVPTX/NVPTXInstrInfo.td

@@ -2467,7 +2467,7 @@ def : Pat<(brcond i32:$a, bb:$target),
 
 // SelectionDAGBuilder::visitSWitchCase() will invert the condition of a
 // conditional branch if the target block is the next block so that the code
-// can fall through to the target block. The invertion is done by 'xor
+// can fall through to the target block. The inversion is done by 'xor
 // condition, 1', which will be translated to (setne condition, -1). Since ptx
 // supports '@!pred bra target', we should use it.
 def : Pat<(brcond (i1 (setne i1:$a, -1)), bb:$target),