clocksource/drivers/vf-pit: Replace raw_readl/writel to readl/writel

The driver uses the raw_readl() and raw_writel() functions. Those are not for MMIO devices. Replace them with readl() and writel() [ dlezcano: Fixed typo in the subject s/reald/readl/ ] Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20250804152344.1109310-2-daniel.lezcano@linaro.org

Author: dlezcano

drivers/clocksource/timer-vf-pit.c

@@ -35,30 +35,30 @@ static unsigned long cycle_per_jiffy;
 
 static inline void pit_timer_enable(void)
 {
-__raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
+writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
 }
 
 static inline void pit_timer_disable(void)
 {
-__raw_writel(0, clkevt_base + PITTCTRL);
+writel(0, clkevt_base + PITTCTRL);
 }
 
 static inline void pit_irq_acknowledge(void)
 {
-__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
+writel(PITTFLG_TIF, clkevt_base + PITTFLG);
 }
 
 static u64 notrace pit_read_sched_clock(void)
 {
-return ~__raw_readl(clksrc_base + PITCVAL);
+return ~readl(clksrc_base + PITCVAL);
 }
 
 static int __init pit_clocksource_init(unsigned long rate)
 {
 /* set the max load value and start the clock source counter */
-__raw_writel(0, clksrc_base + PITTCTRL);
-__raw_writel(~0UL, clksrc_base + PITLDVAL);
-__raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
+writel(0, clksrc_base + PITTCTRL);
+writel(~0UL, clksrc_base + PITLDVAL);
+writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
 
 sched_clock_register(pit_read_sched_clock, 32, rate);
 return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate,
@@ -76,7 +76,7 @@ static int pit_set_next_event(unsigned long delta,
  * hardware requirement.
  */
 pit_timer_disable();
-__raw_writel(delta - 1, clkevt_base + PITLDVAL);
+writel(delta - 1, clkevt_base + PITLDVAL);
 pit_timer_enable();
 
 return 0;
@@ -125,8 +125,8 @@ static struct clock_event_device clockevent_pit = {
 
 static int __init pit_clockevent_init(unsigned long rate, int irq)
 {
-__raw_writel(0, clkevt_base + PITTCTRL);
-__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
+writel(0, clkevt_base + PITTCTRL);
+writel(PITTFLG_TIF, clkevt_base + PITTFLG);
 
 BUG_ON(request_irq(irq, pit_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
  "VF pit timer", &clockevent_pit));
@@ -183,7 +183,7 @@ static int __init pit_timer_init(struct device_node *np)
 cycle_per_jiffy = clk_rate / (HZ);
 
 /* enable the pit module */
-__raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
+writel(~PITMCR_MDIS, timer_base + PITMCR);
 
 ret = pit_clocksource_init(clk_rate);
 if (ret)