[TableGen] Fix regunit superset calculation

Author: jayfoad

lib/Target/AArch64/AArch64GenRegisterInfo.inc

@@ -1229,13 +1229,15 @@ enum RegisterPressureSets {
  FPR128_0to7 = 13,
  GPR64x8Class_with_x8sub_0_in_tcGPRx16x17_with_GPR64x8Class_with_x8sub_7_in_FIXED_REGS = 14,
  PPRorPNR = 15,
- GPR64x8Class_with_x8sub_6_in_tcGPRx16x17_with_GPR64x8Class_with_x8sub_0_in_tcGPRx16x17 = 16,
- GPR64x8Class_with_x8sub_6_in_tcGPRx16x17 = 17,
+ GPR64x8Class_with_x8sub_0_in_tcGPRx16x17_with_FIXED_REGS_with_GPR64x8Class_with_x8sub_7_in_FIXED_REGS = 16,
+ GPR64x8Class_with_x8sub_2_in_tcGPRx16x17_with_GPR64x8Class_with_x8sub_6_in_tcGPRx16x17 = 17,
  FPR16_lo = 18,
  GPR64x8Class_with_x8sub_0_in_tcGPR64 = 19,
- GPR64x8Class_with_x8sub_0_in_tcGPR64_with_GPR64x8Class_with_x8sub_7_in_FIXED_REGS = 20,
- FPR8 = 21,
- GPR32 = 22,
+ GPR64x8Class_with_x8sub_7_in_FIXED_REGS_with_GPR64x8Class_with_x8sub_6_in_tcGPRx16x17_with_GPR64x8Class_with_x8sub_0_in_tcGPRx16x17 = 20,
+ GPR64x8Class_with_x8sub_6_in_tcGPRx16x17_with_GPR64x8Class_with_x8sub_0_in_tcGPRx16x17_with_FIXED_REGS_with_GPR64x8Class_with_x8sub_7_in_FIXED_REGS = 21,
+ GPR64x8Class_with_x8sub_0_in_tcGPR64_with_GPR64x8Class_with_x8sub_7_in_FIXED_REGS = 22,
+ FPR8 = 23,
+ GPR32 = 24,
 };
 } // end namespace AArch64
 
@@ -114098,7 +114100,7 @@ getRegUnitWeight(unsigned RegUnit) const {
 
 // Get the number of dimensions of register pressure.
 unsigned AArch64GenRegisterInfo::getNumRegPressureSets() const {
- return 23;
+ return 25;
 }
 
 // Get the name of this register unit pressure set.
@@ -114121,10 +114123,12 @@ getRegPressureSetName(unsigned Idx) const {
  "FPR128_0to7",
  "GPR64x8Class_with_x8sub_0_in_tcGPRx16x17_with_GPR64x8Class_with_x8sub_7_in_FIXED_REGS",
  "PPRorPNR",
- "GPR64x8Class_with_x8sub_6_in_tcGPRx16x17_with_GPR64x8Class_with_x8sub_0_in_tcGPRx16x17",
- "GPR64x8Class_with_x8sub_6_in_tcGPRx16x17",
+ "GPR64x8Class_with_x8sub_0_in_tcGPRx16x17_with_FIXED_REGS_with_GPR64x8Class_with_x8sub_7_in_FIXED_REGS",
+ "GPR64x8Class_with_x8sub_2_in_tcGPRx16x17_with_GPR64x8Class_with_x8sub_6_in_tcGPRx16x17",
  "FPR16_lo",
  "GPR64x8Class_with_x8sub_0_in_tcGPR64",
+ "GPR64x8Class_with_x8sub_7_in_FIXED_REGS_with_GPR64x8Class_with_x8sub_6_in_tcGPRx16x17_with_GPR64x8Class_with_x8sub_0_in_tcGPRx16x17",
+ "GPR64x8Class_with_x8sub_6_in_tcGPRx16x17_with_GPR64x8Class_with_x8sub_0_in_tcGPRx16x17_with_FIXED_REGS_with_GPR64x8Class_with_x8sub_7_in_FIXED_REGS",
  "GPR64x8Class_with_x8sub_0_in_tcGPR64_with_GPR64x8Class_with_x8sub_7_in_FIXED_REGS",
  "FPR8",
  "GPR32",
@@ -114153,13 +114157,15 @@ getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  14,	// 13: FPR128_0to7
  14,	// 14: GPR64x8Class_with_x8sub_0_in_tcGPRx16x17_with_GPR64x8Class_with_x8sub_7_in_FIXED_REGS
  16,	// 15: PPRorPNR
- 16,	// 16: GPR64x8Class_with_x8sub_6_in_tcGPRx16x17_with_GPR64x8Class_with_x8sub_0_in_tcGPRx16x17
- 18,	// 17: GPR64x8Class_with_x8sub_6_in_tcGPRx16x17
+ 17,	// 16: GPR64x8Class_with_x8sub_0_in_tcGPRx16x17_with_FIXED_REGS_with_GPR64x8Class_with_x8sub_7_in_FIXED_REGS
+ 20,	// 17: GPR64x8Class_with_x8sub_2_in_tcGPRx16x17_with_GPR64x8Class_with_x8sub_6_in_tcGPRx16x17
  22,	// 18: FPR16_lo
  26,	// 19: GPR64x8Class_with_x8sub_0_in_tcGPR64
- 30,	// 20: GPR64x8Class_with_x8sub_0_in_tcGPR64_with_GPR64x8Class_with_x8sub_7_in_FIXED_REGS
- 32,	// 21: FPR8
- 35,	// 22: GPR32
+ 26,	// 20: GPR64x8Class_with_x8sub_7_in_FIXED_REGS_with_GPR64x8Class_with_x8sub_6_in_tcGPRx16x17_with_GPR64x8Class_with_x8sub_0_in_tcGPRx16x17
+ 29,	// 21: GPR64x8Class_with_x8sub_6_in_tcGPRx16x17_with_GPR64x8Class_with_x8sub_0_in_tcGPRx16x17_with_FIXED_REGS_with_GPR64x8Class_with_x8sub_7_in_FIXED_REGS
+ 30,	// 22: GPR64x8Class_with_x8sub_0_in_tcGPR64_with_GPR64x8Class_with_x8sub_7_in_FIXED_REGS
+ 32,	// 23: FPR8
+ 35,	// 24: GPR32
  };
  return PressureLimitTable[Idx];
 }
@@ -114170,23 +114176,23 @@ static const int RCSetsTable[] = {
  /* 2 */ 10, 15, -1,
  /* 5 */ 1, 10, 11, 15, -1,
  /* 10 */ 2, 10, 11, 15, -1,
- /* 15 */ 13, 18, 21, -1,
- /* 19 */ 7, 12, 22, -1,
- /* 23 */ 4, 7, 9, 12, 14, 20, 22, -1,
- /* 31 */ 9, 12, 14, 19, 20, 22, -1,
- /* 38 */ 8, 14, 16, 19, 20, 22, -1,
- /* 45 */ 8, 9, 12, 14, 16, 19, 20, 22, -1,
- /* 54 */ 5, 16, 17, 19, 20, 22, -1,
- /* 61 */ 6, 16, 17, 19, 20, 22, -1,
- /* 68 */ 3, 8, 14, 16, 17, 19, 20, 22, -1,
+ /* 15 */ 13, 18, 23, -1,
+ /* 19 */ 7, 12, 16, 21, 24, -1,
+ /* 25 */ 19, 22, 24, -1,
+ /* 29 */ 4, 7, 9, 12, 14, 16, 20, 21, 22, 24, -1,
+ /* 40 */ 9, 12, 14, 16, 19, 20, 21, 22, 24, -1,
+ /* 50 */ 5, 17, 19, 20, 21, 22, 24, -1,
+ /* 58 */ 6, 17, 19, 20, 21, 22, 24, -1,
+ /* 66 */ 3, 8, 14, 16, 17, 19, 20, 21, 22, 24, -1,
+ /* 77 */ 8, 9, 12, 14, 16, 17, 19, 20, 21, 22, 24, -1,
 };
 
 /// Get the dimensions of register pressure impacted by this register class.
 /// Returns a -1 terminated array of pressure set IDs
 const int *AArch64GenRegisterInfo::
 getRegClassPressureSets(const TargetRegisterClass *RC) const {
  static const uint8_t RCSetStartTable[] = {
- 17,17,3,16,3,3,2,7,2,7,3,3,2,7,2,7,2,7,2,7,5,10,21,17,21,21,21,16,34,54,61,1,19,21,28,34,54,61,21,17,21,21,21,21,28,34,34,34,16,34,19,54,61,19,68,23,19,68,17,16,16,21,16,28,21,28,34,34,34,34,34,54,61,68,23,17,17,16,1,16,15,15,17,16,16,16,16,16,16,17,16,16,16,16,16,16,16,16,16,16,17,17,17,16,16,17,17,16,16,16,16,16,16,15,15,16,16,15,15,15,15,15,1,17,17,16,16,16,16,17,16,17,16,16,16,16,16,16,16,15,15,15,16,16,15,16,15,16,15,15,15,15,16,15,16,15,15,15,15,15,15,15,15,17,17,16,16,16,16,17,16,17,17,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,15,15,15,15,17,17,16,16,16,16,15,16,15,15,16,15,15,15,15,16,15,16,15,16,15,15,15,16,15,16,15,15,15,16,16,15,15,15,15,15,15,15,15,15,15,28,28,28,28,28,28,28,28,34,28,28,28,34,34,34,34,34,28,28,28,28,34,34,34,34,34,34,34,34,34,34,28,34,34,34,34,34,34,34,34,34,34,34,34,34,34,34,34,34,1,34,55,55,55,56,56,34,34,56,55,38,56,55,34,55,34,55,25,0,1,1,1,};
+ 17,17,3,16,3,3,2,7,2,7,3,3,2,7,2,7,2,7,2,7,5,10,23,17,23,23,23,16,25,50,58,1,19,23,26,25,50,58,23,17,23,23,23,23,26,25,25,25,16,25,19,50,58,19,66,29,19,66,17,16,16,23,16,26,23,26,25,25,25,25,25,50,58,66,29,17,17,16,1,16,15,15,17,16,16,16,16,16,16,17,16,16,16,16,16,16,16,16,16,16,17,17,17,16,16,17,17,16,16,16,16,16,16,15,15,16,16,15,15,15,15,15,1,17,17,16,16,16,16,17,16,17,16,16,16,16,16,16,16,15,15,15,16,16,15,16,15,16,15,15,15,15,16,15,16,15,15,15,15,15,15,15,15,17,17,16,16,16,16,17,16,17,17,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,15,15,15,15,17,17,16,16,16,16,15,16,15,15,16,15,15,15,15,16,15,16,15,16,15,15,15,16,15,16,15,15,15,16,16,15,15,15,15,15,15,15,15,15,15,26,26,26,26,26,26,26,26,25,26,26,26,25,25,25,25,25,26,26,26,26,25,25,25,25,25,25,25,25,25,25,26,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,1,25,51,51,51,51,51,25,25,51,51,67,51,51,25,51,25,51,31,0,1,1,1,};
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
 }
 
@@ -114196,7 +114202,7 @@ const int *AArch64GenRegisterInfo::
 getRegUnitPressureSets(unsigned RegUnit) const {
  assert(RegUnit < 103 && "invalid register unit");
  static const uint8_t RUSetStartTable[] = {
- 19,23,1,1,21,1,19,19,21,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,15,15,15,15,15,15,15,15,15,15,15,16,16,16,16,16,16,16,16,17,17,17,17,17,17,17,17,17,17,15,15,15,10,2,2,2,2,2,2,5,5,7,7,7,7,7,7,10,34,34,34,34,56,56,56,56,61,61,61,61,54,54,54,54,68,68,69,69,69,69,45,45,31,31,25,25,23,0,};
+ 19,29,1,1,23,1,19,19,23,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,15,15,15,15,15,15,15,15,15,15,15,16,16,16,16,16,16,16,16,17,17,17,17,17,17,17,17,17,17,15,15,15,10,2,2,2,2,2,2,5,5,7,7,7,7,7,7,10,25,25,25,25,51,51,51,51,58,58,58,58,50,50,50,50,66,66,67,67,67,67,77,77,40,40,31,31,29,0,};
  return &RCSetsTable[RUSetStartTable[RegUnit]];
 }