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razvanlupusoruVijayKandiah
razvanlupusoru
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VijayKandiah
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[mlir][acc] Add acc serial to acc parallel conversion (#170189)
This patch introduces a new transformation pass that converts `acc.serial` constructs into `acc.parallel` constructs with num_gangs(1), num_workers(1), and vector_length(1). The transformation is semantically equivalent since an OpenACC serial region executes sequentially, which is identical to a parallel region with a single gang, worker, and vector. This unification simplifies processing of acc regions by enabling code reuse in later compilation stages. Co-authored-by: Vijay Kandiah <vkandiah@nvidia.com>
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‎mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td‎

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@@ -136,4 +136,20 @@ def ACCImplicitRoutine : Pass<"acc-implicit-routine", "mlir::ModuleOp"> {
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];
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}
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def ACCLegalizeSerial : Pass<"acc-legalize-serial", "mlir::func::FuncOp"> {
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let summary = "Legalize OpenACC serial constructs";
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let description = [{
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This pass converts `acc.serial` constructs into `acc.parallel` constructs
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with `num_gangs(1)`, `num_workers(1)`, and `vector_length(1)`.
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This transformation simplifies processing of acc regions by unifying the
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handling of serial and parallel constructs. Since an OpenACC serial region
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executes sequentially (like a parallel region with a single gang, worker,
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and vector), this conversion is semantically equivalent while enabling code
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reuse in later compilation stages.
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}];
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let dependentDialects = ["mlir::acc::OpenACCDialect",
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"mlir::arith::ArithDialect"];
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}
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#endif // MLIR_DIALECT_OPENACC_TRANSFORMS_PASSES

‎mlir/lib/Dialect/OpenACC/Transforms/ACCLegalizeSerial.cpp‎

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//===- ACCLegalizeSerial.cpp - Legalize ACC Serial region -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass converts acc.serial into acc.parallel with num_gangs(1)
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// num_workers(1) vector_length(1).
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//
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// This transformation simplifies processing of acc regions by unifying the
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// handling of serial and parallel constructs. Since an OpenACC serial region
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// executes sequentially (like a parallel region with a single gang, worker, and
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// vector), this conversion is semantically equivalent while enabling code reuse
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// in later compilation stages.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Dialect/OpenACC/Transforms/Passes.h"
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#include "mlir/Dialect/Arith/IR/Arith.h"
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#include "mlir/Dialect/Func/IR/FuncOps.h"
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#include "mlir/Dialect/OpenACC/OpenACC.h"
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#include "mlir/IR/Builders.h"
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#include "mlir/IR/BuiltinAttributes.h"
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#include "mlir/IR/Location.h"
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#include "mlir/IR/MLIRContext.h"
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#include "mlir/IR/PatternMatch.h"
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#include "mlir/IR/Region.h"
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#include "mlir/IR/Value.h"
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#include "mlir/Support/LLVM.h"
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#include "mlir/Support/LogicalResult.h"
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#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
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#include "llvm/Support/Debug.h"
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namespace mlir {
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namespace acc {
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#define GEN_PASS_DEF_ACCLEGALIZESERIAL
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#include "mlir/Dialect/OpenACC/Transforms/Passes.h.inc"
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} // namespace acc
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} // namespace mlir
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#define DEBUG_TYPE "acc-legalize-serial"
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namespace {
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using namespace mlir;
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struct ACCSerialOpConversion : public OpRewritePattern<acc::SerialOp> {
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using OpRewritePattern<acc::SerialOp>::OpRewritePattern;
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LogicalResult matchAndRewrite(acc::SerialOp serialOp,
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PatternRewriter &rewriter) const override {
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const Location loc = serialOp.getLoc();
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// Create a container holding the constant value of 1 for use as the
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// num_gangs, num_workers, and vector_length attributes.
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llvm::SmallVector<mlir::Value> numValues;
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auto value = arith::ConstantIntOp::create(rewriter, loc, 1, 32);
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numValues.push_back(value);
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// Since num_gangs is specified as both attributes and values, create a
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// segment attribute.
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llvm::SmallVector<int32_t> numGangsSegments;
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numGangsSegments.push_back(numValues.size());
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auto gangSegmentsAttr = rewriter.getDenseI32ArrayAttr(numGangsSegments);
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// Create a device_type attribute set to `none` which ensures that
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// the parallel dimensions specification applies to the default clauses.
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llvm::SmallVector<mlir::Attribute> crtDeviceTypes;
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auto crtDeviceTypeAttr = mlir::acc::DeviceTypeAttr::get(
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rewriter.getContext(), mlir::acc::DeviceType::None);
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crtDeviceTypes.push_back(crtDeviceTypeAttr);
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auto devTypeAttr =
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mlir::ArrayAttr::get(rewriter.getContext(), crtDeviceTypes);
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LLVM_DEBUG(llvm::dbgs() << "acc.serial OP: " << serialOp << "\n");
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// Create a new acc.parallel op with the same operands - except include the
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// num_gangs, num_workers, and vector_length attributes.
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acc::ParallelOp parOp = acc::ParallelOp::create(
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rewriter, loc, serialOp.getAsyncOperands(),
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serialOp.getAsyncOperandsDeviceTypeAttr(), serialOp.getAsyncOnlyAttr(),
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serialOp.getWaitOperands(), serialOp.getWaitOperandsSegmentsAttr(),
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serialOp.getWaitOperandsDeviceTypeAttr(),
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serialOp.getHasWaitDevnumAttr(), serialOp.getWaitOnlyAttr(), numValues,
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gangSegmentsAttr, devTypeAttr, numValues, devTypeAttr, numValues,
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devTypeAttr, serialOp.getIfCond(), serialOp.getSelfCond(),
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serialOp.getSelfAttrAttr(), serialOp.getReductionOperands(),
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serialOp.getPrivateOperands(), serialOp.getFirstprivateOperands(),
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serialOp.getDataClauseOperands(), serialOp.getDefaultAttrAttr(),
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serialOp.getCombinedAttr());
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parOp.getRegion().takeBody(serialOp.getRegion());
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LLVM_DEBUG(llvm::dbgs() << "acc.parallel OP: " << parOp << "\n");
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rewriter.replaceOp(serialOp, parOp);
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return success();
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}
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};
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class ACCLegalizeSerial
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: public mlir::acc::impl::ACCLegalizeSerialBase<ACCLegalizeSerial> {
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public:
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using ACCLegalizeSerialBase<ACCLegalizeSerial>::ACCLegalizeSerialBase;
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void runOnOperation() override {
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func::FuncOp funcOp = getOperation();
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MLIRContext *context = funcOp.getContext();
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RewritePatternSet patterns(context);
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patterns.insert<ACCSerialOpConversion>(context);
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(void)applyPatternsGreedily(funcOp, std::move(patterns));
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}
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};
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} // namespace

‎mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt‎

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@@ -2,6 +2,7 @@ add_mlir_dialect_library(MLIROpenACCTransforms
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ACCImplicitData.cpp
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ACCImplicitDeclare.cpp
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ACCImplicitRoutine.cpp
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ACCLegalizeSerial.cpp
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LegalizeDataValues.cpp
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ADDITIONAL_HEADER_DIRS

‎mlir/test/Dialect/OpenACC/legalize-serial.mlir‎

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// RUN: mlir-opt %s -acc-legalize-serial | FileCheck %s
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acc.private.recipe @privatization_memref_10_f32 : memref<10xf32> init {
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^bb0(%arg0: memref<10xf32>):
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%0 = memref.alloc() : memref<10xf32>
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acc.yield %0 : memref<10xf32>
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} destroy {
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^bb0(%arg0: memref<10xf32>):
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memref.dealloc %arg0 : memref<10xf32>
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acc.terminator
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}
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acc.private.recipe @privatization_memref_10_10_f32 : memref<10x10xf32> init {
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^bb0(%arg0: memref<10x10xf32>):
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%0 = memref.alloc() : memref<10x10xf32>
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acc.yield %0 : memref<10x10xf32>
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} destroy {
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^bb0(%arg0: memref<10x10xf32>):
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memref.dealloc %arg0 : memref<10x10xf32>
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acc.terminator
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}
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acc.firstprivate.recipe @firstprivatization_memref_10xf32 : memref<10xf32> init {
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^bb0(%arg0: memref<10xf32>):
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%0 = memref.alloc() : memref<10xf32>
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acc.yield %0 : memref<10xf32>
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} copy {
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^bb0(%arg0: memref<10xf32>, %arg1: memref<10xf32>):
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acc.terminator
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} destroy {
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^bb0(%arg0: memref<10xf32>):
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memref.dealloc %arg0 : memref<10xf32>
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acc.terminator
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}
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acc.reduction.recipe @reduction_add_i64 : i64 reduction_operator<add> init {
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^bb0(%0: i64):
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%1 = arith.constant 0 : i64
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acc.yield %1 : i64
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} combiner {
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^bb0(%0: i64, %1: i64):
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%2 = arith.addi %0, %1 : i64
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acc.yield %2 : i64
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}
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acc.reduction.recipe @reduction_add_memref_i64 : memref<i64> reduction_operator<add> init {
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^bb0(%arg0: memref<i64>):
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%0 = memref.alloca() : memref<i64>
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%c0 = arith.constant 0 : i64
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memref.store %c0, %0[] : memref<i64>
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acc.yield %0 : memref<i64>
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} combiner {
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^bb0(%arg0: memref<i64>, %arg1: memref<i64>):
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%0 = memref.load %arg0[] : memref<i64>
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%1 = memref.load %arg1[] : memref<i64>
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%2 = arith.addi %0, %1 : i64
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memref.store %2, %arg0[] : memref<i64>
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acc.terminator
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}
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// CHECK: func.func @testserialop(%[[VAL_0:.*]]: memref<10xf32>, %[[VAL_1:.*]]: memref<10xf32>, %[[VAL_2:.*]]: memref<10x10xf32>) {
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// CHECK: %[[VAL_3:.*]] = arith.constant 1 : i64
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// CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32
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// CHECK: %[[VAL_5:.*]] = arith.constant 1 : index
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// CHECK: acc.parallel async(%[[VAL_3]] : i64) num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) {
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// CHECK: }
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// CHECK: acc.parallel async(%[[VAL_4]] : i32) num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) {
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// CHECK: }
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// CHECK: acc.parallel async(%[[VAL_5]] : index) num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) {
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// CHECK: }
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// CHECK: acc.parallel num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) wait({%[[VAL_3]] : i64}) {
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// CHECK: }
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// CHECK: acc.parallel num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) wait({%[[VAL_4]] : i32}) {
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// CHECK: }
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// CHECK: acc.parallel num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) wait({%[[VAL_5]] : index}) {
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// CHECK: }
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// CHECK: acc.parallel num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) wait({%[[VAL_3]] : i64, %[[VAL_4]] : i32, %[[VAL_5]] : index}) {
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// CHECK: }
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// CHECK: %[[VAL_6:.*]] = acc.firstprivate varPtr(%[[VAL_1]] : memref<10xf32>) recipe(@firstprivatization_memref_10xf32) -> memref<10xf32>
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// CHECK: %[[VAL_9:.*]] = acc.private varPtr(%[[VAL_2]] : memref<10x10xf32>) recipe(@privatization_memref_10_10_f32) -> memref<10x10xf32>
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// CHECK: acc.parallel firstprivate(%[[VAL_6]] : memref<10xf32>) num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) private(%[[VAL_9]] : memref<10x10xf32>) vector_length(%[[VAL_4]] : i32) {
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// CHECK: }
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// CHECK: %[[VAL_7:.*]] = acc.copyin varPtr(%[[VAL_0]] : memref<10xf32>) -> memref<10xf32> {dataClause = #acc<data_clause acc_copy>}
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// CHECK: acc.parallel dataOperands(%[[VAL_7]] : memref<10xf32>) num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) {
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// CHECK: }
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// CHECK: %[[I64MEM:.*]] = memref.alloca() : memref<i64>
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// CHECK: memref.store %[[VAL_3]], %[[I64MEM]][] : memref<i64>
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// CHECK: %[[VAL_10:.*]] = acc.reduction varPtr(%[[I64MEM]] : memref<i64>) recipe(@reduction_add_memref_i64) -> memref<i64>
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// CHECK: acc.parallel num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) reduction(%[[VAL_10]] : memref<i64>) {
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// CHECK: }
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// CHECK: acc.parallel combined(loop) num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) {
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// CHECK: acc.loop combined(serial) control(%{{.*}} : index) = (%[[VAL_5]] : index) to (%[[VAL_5]] : index) step (%[[VAL_5]] : index) {
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// CHECK: acc.yield
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// CHECK: } attributes {seq = [#acc.device_type<none>]}
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// CHECK: acc.terminator
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// CHECK: }
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// CHECK: acc.parallel num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) {
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// CHECK: } attributes {defaultAttr = #acc<defaultvalue none>}
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// CHECK: acc.parallel num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) {
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// CHECK: } attributes {defaultAttr = #acc<defaultvalue present>}
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// CHECK: acc.parallel num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) {
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// CHECK: }
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// CHECK: acc.parallel num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) {
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// CHECK: }
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// CHECK: acc.parallel num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) {
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// CHECK: } attributes {selfAttr}
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// CHECK: acc.parallel num_gangs({%[[VAL_4]] : i32}) num_workers(%[[VAL_4]] : i32) vector_length(%[[VAL_4]] : i32) {
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// CHECK: acc.yield
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// CHECK: } attributes {selfAttr}
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// CHECK: return
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// CHECK: }
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func.func @testserialop(%a: memref<10xf32>, %b: memref<10xf32>, %c: memref<10x10xf32>) -> () {
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%i64value = arith.constant 1 : i64
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%i32value = arith.constant 1 : i32
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%idxValue = arith.constant 1 : index
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acc.serial async(%i64value: i64) {
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}
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acc.serial async(%i32value: i32) {
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}
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acc.serial async(%idxValue: index) {
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}
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acc.serial wait({%i64value: i64}) {
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}
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acc.serial wait({%i32value: i32}) {
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}
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acc.serial wait({%idxValue: index}) {
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}
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acc.serial wait({%i64value : i64, %i32value : i32, %idxValue : index}) {
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}
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%firstprivate = acc.firstprivate varPtr(%b : memref<10xf32>) recipe(@firstprivatization_memref_10xf32) -> memref<10xf32>
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%c_private = acc.private varPtr(%c : memref<10x10xf32>) recipe(@privatization_memref_10_10_f32) -> memref<10x10xf32>
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acc.serial private(%c_private : memref<10x10xf32>) firstprivate(%firstprivate : memref<10xf32>) {
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}
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%copyinfromcopy = acc.copyin varPtr(%a : memref<10xf32>) -> memref<10xf32> {dataClause = #acc<data_clause acc_copy>}
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acc.serial dataOperands(%copyinfromcopy : memref<10xf32>) {
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}
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%i64mem = memref.alloca() : memref<i64>
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memref.store %i64value, %i64mem[] : memref<i64>
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%i64reduction = acc.reduction varPtr(%i64mem : memref<i64>) recipe(@reduction_add_memref_i64) -> memref<i64>
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acc.serial reduction(%i64reduction : memref<i64>) {
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}
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acc.serial combined(loop) {
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acc.loop combined(serial) control(%arg3 : index) = (%idxValue : index) to (%idxValue : index) step (%idxValue : index) {
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acc.yield
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} attributes {seq = [#acc.device_type<none>]}
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acc.terminator
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}
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acc.serial {
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} attributes {defaultAttr = #acc<defaultvalue none>}
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acc.serial {
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} attributes {defaultAttr = #acc<defaultvalue present>}
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acc.serial {
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} attributes {asyncAttr}
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acc.serial {
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} attributes {waitAttr}
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acc.serial {
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} attributes {selfAttr}
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acc.serial {
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acc.yield
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} attributes {selfAttr}
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return
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}
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