[LV] Add test for missed interleaving after narrowing interleave groups.

Add extra test coverage for #149706. The added loop should be interleaved, after narrowing interleave groups, which requires moving the transform earlier.

Author: fhahn

llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll

@@ -437,4 +437,64 @@ exit:
  ret void
 }
 
+; FIXME: We should interleave by 2 after narrowing interleave groups to saturate
+; load/store units.
+define void @test_interleave_after_narrowing(i32 %n, ptr %x, ptr noalias %y) {
+; CHECK-LABEL: define void @test_interleave_after_narrowing(
+; CHECK-SAME: i32 [[N:%.*]], ptr [[X:%.*]], ptr noalias [[Y:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw float, ptr [[X]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = fneg <4 x float> [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw float, ptr [[Y]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: store <4 x float> [[TMP1]], ptr [[TMP2]], align 4
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256
+; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br [[EXIT:label %.*]]
+; CHECK: [[SCALAR_PH]]:
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %gep.x = getelementptr inbounds nuw float, ptr %x, i64 %iv
+ %l.x = load float, ptr %gep.x, align 4
+ %neg.0 = fneg float %l.x
+ %gep.y = getelementptr inbounds nuw float, ptr %y, i64 %iv
+ store float %neg.0, ptr %gep.y, align 4
+ %iv.1 = or disjoint i64 %iv, 1
+ %gep.x.1 = getelementptr inbounds nuw float, ptr %x, i64 %iv.1
+ %l.x.1 = load float, ptr %gep.x.1, align 4
+ %neg.1 = fneg float %l.x.1
+ %gep.y.1 = getelementptr inbounds nuw float, ptr %y, i64 %iv.1
+ store float %neg.1, ptr %gep.y.1, align 4
+ %iv.2 = or disjoint i64 %iv, 2
+ %gep.x.2 = getelementptr inbounds nuw float, ptr %x, i64 %iv.2
+ %l.x.2 = load float, ptr %gep.x.2, align 4
+ %neg.2 = fneg float %l.x.2
+ %gep.y.2 = getelementptr inbounds nuw float, ptr %y, i64 %iv.2
+ store float %neg.2, ptr %gep.y.2, align 4
+ %iv.3 = or disjoint i64 %iv, 3
+ %gep.x.3 = getelementptr inbounds nuw float, ptr %x, i64 %iv.3
+ %l.x.3 = load float, ptr %gep.x.3, align 4
+ %neg.3 = fneg float %l.x.3
+ %gep.y.3 = getelementptr inbounds nuw float, ptr %y, i64 %iv.3
+ store float %neg.3, ptr %gep.y.3, align 4
+ %iv.next = add nuw nsw i64 %iv, 4
+ %ec = icmp samesign ult i64 %iv, 1020
+ br i1 %ec, label %loop, label %exit
+
+exit:
+ ret void
+}
+
 attributes #0 = { "target-cpu"="neoverse-v2" }