[BPF] Support signed division at cpu v1 with constant divisor

The motivation example likes below $ cat t1.c struct S { int var[3]; }; int foo1 (struct S *a, struct S *b) { return a - b; } For cpu v1/v2/v3, the compilation will fail with the following errors: $ clang --target=bpf -O2 -c t1.c -mcpu=v3 t1.c:4:5: error: unsupported signed division, please convert to unsigned div/mod. 4 | int foo1 (struct S *a, struct S *b) | ^ 1 error generated. The reason is that sdiv/smod is supported at -mcpu=v4. At cpu v1/v2/v3, only udiv/umod is supported. But the above example (for func foo1()) is reasonable common and user has to workaround the compilation failure by using udiv with conditionals. For x86, for the above t1.c, compile and dump the asm code like below: $ clang -O2 -c t1.c && llvm-objdump -d t1.o 0000000000000000 <foo1>: 0: 48 29 f7 subq %rsi, %rdi 3: 48 c1 ef 02 shrq $0x2, %rdi 7: 69 c7 ab aa aa aa imull $0xaaaaaaab, %edi, %eax # imm = 0xAAAAAAAB d: c3 retq Basically sdiv can be replaced with sub, shr and imul. Latest gcc-bpf is also able to generate code similar to x86 with -mcpu=v1. See https://godbolt.org/z/feP9ETbjj So let us add clang support for sdiv (constant divisor) as well at -mcpu=v1. But we still want to keep udiv untouched at -mcpu=v1. One more parameter "bool IsSigned" is added to isIntDivCheap(). The "IsSigned" parameter is used only by BPF backend to ensure udiv not impacted. Note that only 32-bit sdiv (constant divisor) can be converted into sub/shr/imul. 64-bit sdiv (constant divisor) cannot be converted since bpf does not support 64-bit multiplication without potential overflow.

Author: Yonghong Song

llvm/include/llvm/CodeGen/BasicTTIImpl.h

@@ -565,7 +565,12 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
  if (!isa<ConstantInt>(Inst.getOperand(1)))
  return false;
  EVT VT = getTLI()->getValueType(DL, Inst.getType());
- return !getTLI()->isIntDivCheap(VT, Fn.getAttributes());
+
+ bool IsSigned = true;
+ if (Inst.getOpcode() == Instruction::SDiv ||
+ Inst.getOpcode() == Instruction::SRem)
+ IsSigned = false;
+ return !getTLI()->isIntDivCheap(VT, IsSigned, Fn.getAttributes());
  }
  };
 

llvm/include/llvm/CodeGen/TargetLowering.h

@@ -549,7 +549,9 @@ class TargetLoweringBase {
  /// several shifts, adds, and multiplies for this target.
  /// The definition of "cheaper" may depend on whether we're optimizing
  /// for speed or for size.
- virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
+ virtual bool isIntDivCheap(EVT VT, bool IsSigned, AttributeList Attr) const {
+ return false;
+ }
 
  /// Return true if the target can handle a standalone remainder operation.
  virtual bool hasStandaloneRem(EVT VT) const {

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

@@ -5376,7 +5376,7 @@ bool CombinerHelper::matchUDivByConst(MachineInstr &MI) {
  const auto &TLI = getTargetLowering();
  LLVMContext &Ctx = MF.getFunction().getContext();
  auto &DL = MF.getDataLayout();
- if (TLI.isIntDivCheap(getApproximateEVTForLLT(DstTy, DL, Ctx), Attr))
+ if (TLI.isIntDivCheap(getApproximateEVTForLLT(DstTy, DL, Ctx), false, Attr))
  return false;
 
  // Don't do this for minsize because the instruction sequence is usually
@@ -5426,7 +5426,7 @@ bool CombinerHelper::matchSDivByConst(MachineInstr &MI) {
  const auto &TLI = getTargetLowering();
  LLVMContext &Ctx = MF.getFunction().getContext();
  auto &DL = MF.getDataLayout();
- if (TLI.isIntDivCheap(getApproximateEVTForLLT(DstTy, DL, Ctx), Attr))
+ if (TLI.isIntDivCheap(getApproximateEVTForLLT(DstTy, DL, Ctx), true, Attr))
  return false;
 
  // Don't do this for minsize because the instruction sequence is usually

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -4844,7 +4844,7 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
  // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
  // true. Otherwise, we break the simplification logic in visitREM().
  AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
- if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
+ if (!N1C || TLI.isIntDivCheap(N->getValueType(0), true, Attr))
  if (SDValue DivRem = useDivRem(N))
  return DivRem;
 
@@ -4929,7 +4929,7 @@ SDValue DAGCombiner::visitSDIVLike(SDValue N0, SDValue N1, SDNode *N) {
  // trade-offs.
  AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
  if (isConstantOrConstantVector(N1) &&
- !TLI.isIntDivCheap(N->getValueType(0), Attr))
+ !TLI.isIntDivCheap(N->getValueType(0), true, Attr))
  if (SDValue Op = BuildSDIV(N))
  return Op;
 
@@ -4984,7 +4984,7 @@ SDValue DAGCombiner::visitUDIV(SDNode *N) {
  // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
  // true. Otherwise, we break the simplification logic in visitREM().
  AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
- if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
+ if (!N1C || TLI.isIntDivCheap(N->getValueType(0), false, Attr))
  if (SDValue DivRem = useDivRem(N))
  return DivRem;
 
@@ -5033,7 +5033,7 @@ SDValue DAGCombiner::visitUDIVLike(SDValue N0, SDValue N1, SDNode *N) {
  // fold (udiv x, c) -> alternate
  AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
  if (isConstantOrConstantVector(N1) &&
- !TLI.isIntDivCheap(N->getValueType(0), Attr))
+ !TLI.isIntDivCheap(N->getValueType(0), false, Attr))
  if (SDValue Op = BuildUDIV(N))
  return Op;
 
@@ -5115,7 +5115,7 @@ SDValue DAGCombiner::visitREM(SDNode *N) {
  // by skipping the simplification if isIntDivCheap(). When div is not cheap,
  // combine will not return a DIVREM. Regardless, checking cheapness here
  // makes sense since the simplification results in fatter code.
- if (DAG.isKnownNeverZero(N1) && !TLI.isIntDivCheap(VT, Attr)) {
+ if (DAG.isKnownNeverZero(N1) && !TLI.isIntDivCheap(VT, isSigned, Attr)) {
  if (isSigned) {
  // check if we can build faster implementation for srem
  if (SDValue OptimizedRem = buildOptimizedSREM(N0, N1, N))

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -5377,11 +5377,13 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
  N0.hasOneUse() && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
  // When division is cheap or optimizing for minimum size,
  // fall through to DIVREM creation by skipping this fold.
- if (!isIntDivCheap(VT, Attr) && !Attr.hasFnAttr(Attribute::MinSize)) {
- if (N0.getOpcode() == ISD::UREM) {
+ bool IsSigned = N0.getOpcode() == ISD::SREM;
+ if (!isIntDivCheap(VT, IsSigned, Attr) &&
+ !Attr.hasFnAttr(Attribute::MinSize)) {
+ if (!IsSigned) {
  if (SDValue Folded = buildUREMEqFold(VT, N0, N1, Cond, DCI, dl))
  return Folded;
- } else if (N0.getOpcode() == ISD::SREM) {
+ } else {
  if (SDValue Folded = buildSREMEqFold(VT, N0, N1, Cond, DCI, dl))
  return Folded;
  }
@@ -6233,7 +6235,7 @@ SDValue TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
  SelectionDAG &DAG,
  SmallVectorImpl<SDNode *> &Created) const {
  AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
- if (isIntDivCheap(N->getValueType(0), Attr))
+ if (isIntDivCheap(N->getValueType(0), true, Attr))
  return SDValue(N, 0); // Lower SDIV as SDIV
  return SDValue();
 }
@@ -6243,7 +6245,7 @@ TargetLowering::BuildSREMPow2(SDNode *N, const APInt &Divisor,
  SelectionDAG &DAG,
  SmallVectorImpl<SDNode *> &Created) const {
  AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
- if (isIntDivCheap(N->getValueType(0), Attr))
+ if (isIntDivCheap(N->getValueType(0), true, Attr))
  return SDValue(N, 0); // Lower SREM as SREM
  return SDValue();
 }

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -18544,7 +18544,7 @@ AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
  SelectionDAG &DAG,
  SmallVectorImpl<SDNode *> &Created) const {
  AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
- if (isIntDivCheap(N->getValueType(0), Attr))
+ if (isIntDivCheap(N->getValueType(0), true, Attr))
  return SDValue(N, 0); // Lower SDIV as SDIV
 
  EVT VT = N->getValueType(0);
@@ -18574,7 +18574,7 @@ AArch64TargetLowering::BuildSREMPow2(SDNode *N, const APInt &Divisor,
  SelectionDAG &DAG,
  SmallVectorImpl<SDNode *> &Created) const {
  AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
- if (isIntDivCheap(N->getValueType(0), Attr))
+ if (isIntDivCheap(N->getValueType(0), true, Attr))
  return SDValue(N, 0); // Lower SREM as SREM
 
  EVT VT = N->getValueType(0);
@@ -27816,7 +27816,8 @@ void AArch64TargetLowering::insertCopiesSplitCSR(
  }
 }
 
-bool AArch64TargetLowering::isIntDivCheap(EVT VT, AttributeList Attr) const {
+bool AArch64TargetLowering::isIntDivCheap(EVT VT, bool IsSigned,
+ AttributeList Attr) const {
  // Integer division on AArch64 is expensive. However, when aggressively
  // optimizing for code size, we prefer to use a div instruction, as it is
  // usually smaller than the alternative sequence.

llvm/lib/Target/AArch64/AArch64ISelLowering.h

@@ -845,7 +845,7 @@ class AArch64TargetLowering : public TargetLowering {
  return AArch64::X1;
  }
 
- bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
+ bool isIntDivCheap(EVT VT, bool IsSigned, AttributeList Attr) const override;
 
  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
  const MachineFunction &MF) const override {

llvm/lib/Target/BPF/BPFISelLowering.cpp

@@ -238,6 +238,11 @@ bool BPFTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
  return TargetLoweringBase::isZExtFree(Val, VT2);
 }
 
+bool BPFTargetLowering::isIntDivCheap(EVT VT, bool IsSigned,
+ AttributeList Attr) const {
+ return (HasMovsx || !IsSigned) ? true : false;
+}
+
 BPFTargetLowering::ConstraintType
 BPFTargetLowering::getConstraintType(StringRef Constraint) const {
  if (Constraint.size() == 1) {

llvm/lib/Target/BPF/BPFISelLowering.h

@@ -118,7 +118,7 @@ class BPFTargetLowering : public TargetLowering {
  return Op.size() >= 8 ? MVT::i64 : MVT::i32;
  }
 
- bool isIntDivCheap(EVT VT, AttributeList Attr) const override { return true; }
+ bool isIntDivCheap(EVT VT, bool IsSigned, AttributeList Attr) const override;
 
  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
  Type *Ty) const override {

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -12680,7 +12680,7 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
  // to multiply by magic constant.
  AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
  if (N->getOperand(1).getOpcode() == ISD::Constant &&
- !isIntDivCheap(N->getValueType(0), Attr))
+ !isIntDivCheap(N->getValueType(0), N->getOpcode() == ISD::SDIV, Attr))
  return;
 
  // If the input is i32, use ANY_EXTEND since the W instructions don't read
@@ -21275,7 +21275,8 @@ SDValue RISCVTargetLowering::joinRegisterPartsIntoValue(
  return SDValue();
 }
 
-bool RISCVTargetLowering::isIntDivCheap(EVT VT, AttributeList Attr) const {
+bool RISCVTargetLowering::isIntDivCheap(EVT VT, bool IsSigned,
+ AttributeList Attr) const {
  // When aggressively optimizing for code size, we prefer to use a div
  // instruction, as it is usually smaller than the alternative sequence.
  // TODO: Add vector division?
@@ -21745,7 +21746,7 @@ RISCVTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
  SelectionDAG &DAG,
  SmallVectorImpl<SDNode *> &Created) const {
  AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
- if (isIntDivCheap(N->getValueType(0), Attr))
+ if (isIntDivCheap(N->getValueType(0), true, Attr))
  return SDValue(N, 0); // Lower SDIV as SDIV
 
  // Only perform this transform if short forward branch opt is supported.