Skip to content

Commit f7e611c

Browse files
paperchalicepaperchalice
committed
[PowerPC] Remove NoInfsFPMath uses
1 parent 93d445c commit f7e611c

File tree

5 files changed

+647
-1121
lines changed

5 files changed

+647
-1121
lines changed

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8326,7 +8326,7 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
83268326
// general, fsel-based lowering of select is a finite-math-only optimization.
83278327
// For more information, see section F.3 of the 2.06 ISA specification.
83288328
// With ISA 3.0
8329-
if ((!DAG.getTarget().Options.NoInfsFPMath && !Flags.hasNoInfs()) ||
8329+
if (!Flags.hasNoInfs() ||
83308330
(!DAG.getTarget().Options.NoNaNsFPMath && !Flags.hasNoNaNs()) ||
83318331
ResVT == MVT::f128)
83328332
return Op;

‎llvm/test/CodeGen/PowerPC/change-no-infs.ll‎

Lines changed: 0 additions & 67 deletions
This file was deleted.

‎llvm/test/CodeGen/PowerPC/fsel.ll‎

Lines changed: 125 additions & 70 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
11
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
2-
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=-vsx | FileCheck -check-prefix=CHECK-FM %s
3-
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=+vsx | FileCheck -check-prefix=CHECK-FM-VSX %s
2+
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-nans-fp-math -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
43
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
54
target triple = "powerpc64-unknown-linux-gnu"
65

@@ -13,14 +12,21 @@ entry:
1312
; CHECK: @zerocmp1
1413
; CHECK-NOT: fsel
1514
; CHECK: blr
15+
}
16+
17+
define double @zerocmp1_finite(double %a, double %y, double %z) #0 {
18+
entry:
19+
%cmp = fcmp ninf nnan ult double %a, 0.000000e+00
20+
%z.y = select i1 %cmp, double %z, double %y
21+
ret double %z.y
1622

17-
; CHECK-FM: @zerocmp1
18-
; CHECK-FM: fsel 1, 1, 2, 3
19-
; CHECK-FM: blr
23+
; CHECK: @zerocmp1_finite
24+
; CHECK: fsel 1, 1, 2, 3
25+
; CHECK: blr
2026

21-
; CHECK-FM-VSX: @zerocmp1
22-
; CHECK-FM-VSX: fsel 1, 1, 2, 3
23-
; CHECK-FM-VSX: blr
27+
; CHECK-VSX: @zerocmp1_finite
28+
; CHECK-VSX: fsel 1, 1, 2, 3
29+
; CHECK-VSX: blr
2430
}
2531

2632
define double @zerocmp2(double %a, double %y, double %z) #0 {
@@ -32,16 +38,23 @@ entry:
3238
; CHECK: @zerocmp2
3339
; CHECK-NOT: fsel
3440
; CHECK: blr
41+
}
42+
43+
define double @zerocmp2_finite(double %a, double %y, double %z) #0 {
44+
entry:
45+
%cmp = fcmp ninf nnan ogt double %a, 0.000000e+00
46+
%y.z = select i1 %cmp, double %y, double %z
47+
ret double %y.z
3548

36-
; CHECK-FM: @zerocmp2
37-
; CHECK-FM: fneg [[REG:[0-9]+]], 1
38-
; CHECK-FM: fsel 1, [[REG]], 3, 2
39-
; CHECK-FM: blr
49+
; CHECK: @zerocmp2_finite
50+
; CHECK: fneg [[REG:[0-9]+]], 1
51+
; CHECK: fsel 1, [[REG]], 3, 2
52+
; CHECK: blr
4053

41-
; CHECK-FM-VSX: @zerocmp2
42-
; CHECK-FM-VSX: xsnegdp [[REG:[0-9]+]], 1
43-
; CHECK-FM-VSX: fsel 1, [[REG]], 3, 2
44-
; CHECK-FM-VSX: blr
54+
; CHECK-VSX: @zerocmp2_finite
55+
; CHECK-VSX: xsnegdp [[REG:[0-9]+]], 1
56+
; CHECK-VSX: fsel 1, [[REG]], 3, 2
57+
; CHECK-VSX: blr
4558
}
4659

4760
define double @zerocmp3(double %a, double %y, double %z) #0 {
@@ -53,18 +66,25 @@ entry:
5366
; CHECK: @zerocmp3
5467
; CHECK-NOT: fsel
5568
; CHECK: blr
69+
}
70+
71+
define double @zerocmp3_finite(double %a, double %y, double %z) #0 {
72+
entry:
73+
%cmp = fcmp ninf nnan oeq double %a, 0.000000e+00
74+
%y.z = select i1 %cmp, double %y, double %z
75+
ret double %y.z
5676

57-
; CHECK-FM: @zerocmp3
58-
; CHECK-FM: fsel [[REG:[0-9]+]], 1, 2, 3
59-
; CHECK-FM: fneg [[REG2:[0-9]+]], 1
60-
; CHECK-FM: fsel 1, [[REG2]], [[REG]], 3
61-
; CHECK-FM: blr
77+
; CHECK: @zerocmp3_finite
78+
; CHECK: fsel [[REG:[0-9]+]], 1, 2, 3
79+
; CHECK: fneg [[REG2:[0-9]+]], 1
80+
; CHECK: fsel 1, [[REG2]], [[REG]], 3
81+
; CHECK: blr
6282

63-
; CHECK-FM-VSX: @zerocmp3
64-
; CHECK-FM-VSX: fsel [[REG:[0-9]+]], 1, 2, 3
65-
; CHECK-FM-VSX: xsnegdp [[REG2:[0-9]+]], 1
66-
; CHECK-FM-VSX: fsel 1, [[REG2]], [[REG]], 3
67-
; CHECK-FM-VSX: blr
83+
; CHECK-VSX: @zerocmp3_finite
84+
; CHECK-VSX: fsel [[REG:[0-9]+]], 1, 2, 3
85+
; CHECK-VSX: xsnegdp [[REG2:[0-9]+]], 1
86+
; CHECK-VSX: fsel 1, [[REG2]], [[REG]], 3
87+
; CHECK-VSX: blr
6888
}
6989

7090
define double @min1(double %a, double %b) #0 {
@@ -76,16 +96,23 @@ entry:
7696
; CHECK: @min1
7797
; CHECK-NOT: fsel
7898
; CHECK: blr
99+
}
100+
101+
define double @min1_finite(double %a, double %b) #0 {
102+
entry:
103+
%cmp = fcmp ninf nnan ole double %a, %b
104+
%cond = select i1 %cmp, double %a, double %b
105+
ret double %cond
79106

80-
; CHECK-FM: @min1
81-
; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
82-
; CHECK-FM: fsel 1, [[REG]], 1, 2
83-
; CHECK-FM: blr
107+
; CHECK: @min1_finite
108+
; CHECK: fsub [[REG:[0-9]+]], 2, 1
109+
; CHECK: fsel 1, [[REG]], 1, 2
110+
; CHECK: blr
84111

85-
; CHECK-FM-VSX: @min1
86-
; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1
87-
; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
88-
; CHECK-FM-VSX: blr
112+
; CHECK-VSX: @min1_finite
113+
; CHECK-VSX: xssubdp [[REG:[0-9]+]], 2, 1
114+
; CHECK-VSX: fsel 1, [[REG]], 1, 2
115+
; CHECK-VSX: blr
89116
}
90117

91118
define double @max1(double %a, double %b) #0 {
@@ -97,16 +124,23 @@ entry:
97124
; CHECK: @max1
98125
; CHECK-NOT: fsel
99126
; CHECK: blr
127+
}
128+
129+
define double @max1_finite(double %a, double %b) #0 {
130+
entry:
131+
%cmp = fcmp ninf nnan oge double %a, %b
132+
%cond = select i1 %cmp, double %a, double %b
133+
ret double %cond
100134

101-
; CHECK-FM: @max1
102-
; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
103-
; CHECK-FM: fsel 1, [[REG]], 1, 2
104-
; CHECK-FM: blr
135+
; CHECK: @max1_finite
136+
; CHECK: fsub [[REG:[0-9]+]], 1, 2
137+
; CHECK: fsel 1, [[REG]], 1, 2
138+
; CHECK: blr
105139

106-
; CHECK-FM-VSX: @max1
107-
; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
108-
; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
109-
; CHECK-FM-VSX: blr
140+
; CHECK-VSX: @max1_finite
141+
; CHECK-VSX: xssubdp [[REG:[0-9]+]], 1, 2
142+
; CHECK-VSX: fsel 1, [[REG]], 1, 2
143+
; CHECK-VSX: blr
110144
}
111145

112146
define double @cmp1(double %a, double %b, double %y, double %z) #0 {
@@ -118,16 +152,23 @@ entry:
118152
; CHECK: @cmp1
119153
; CHECK-NOT: fsel
120154
; CHECK: blr
155+
}
156+
157+
define double @cmp1_finite(double %a, double %b, double %y, double %z) #0 {
158+
entry:
159+
%cmp = fcmp ninf nnan ult double %a, %b
160+
%z.y = select i1 %cmp, double %z, double %y
161+
ret double %z.y
121162

122-
; CHECK-FM: @cmp1
123-
; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
124-
; CHECK-FM: fsel 1, [[REG]], 3, 4
125-
; CHECK-FM: blr
163+
; CHECK: @cmp1_finite
164+
; CHECK: fsub [[REG:[0-9]+]], 1, 2
165+
; CHECK: fsel 1, [[REG]], 3, 4
166+
; CHECK: blr
126167

127-
; CHECK-FM-VSX: @cmp1
128-
; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
129-
; CHECK-FM-VSX: fsel 1, [[REG]], 3, 4
130-
; CHECK-FM-VSX: blr
168+
; CHECK-VSX: @cmp1_finite
169+
; CHECK-VSX: xssubdp [[REG:[0-9]+]], 1, 2
170+
; CHECK-VSX: fsel 1, [[REG]], 3, 4
171+
; CHECK-VSX: blr
131172
}
132173

133174
define double @cmp2(double %a, double %b, double %y, double %z) #0 {
@@ -139,16 +180,23 @@ entry:
139180
; CHECK: @cmp2
140181
; CHECK-NOT: fsel
141182
; CHECK: blr
183+
}
184+
185+
define double @cmp2_finite(double %a, double %b, double %y, double %z) #0 {
186+
entry:
187+
%cmp = fcmp ninf nnan ogt double %a, %b
188+
%y.z = select i1 %cmp, double %y, double %z
189+
ret double %y.z
142190

143-
; CHECK-FM: @cmp2
144-
; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
145-
; CHECK-FM: fsel 1, [[REG]], 4, 3
146-
; CHECK-FM: blr
191+
; CHECK: @cmp2_finite
192+
; CHECK: fsub [[REG:[0-9]+]], 2, 1
193+
; CHECK: fsel 1, [[REG]], 4, 3
194+
; CHECK: blr
147195

148-
; CHECK-FM-VSX: @cmp2
149-
; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1
150-
; CHECK-FM-VSX: fsel 1, [[REG]], 4, 3
151-
; CHECK-FM-VSX: blr
196+
; CHECK-VSX: @cmp2_finite
197+
; CHECK-VSX: xssubdp [[REG:[0-9]+]], 2, 1
198+
; CHECK-VSX: fsel 1, [[REG]], 4, 3
199+
; CHECK-VSX: blr
152200
}
153201

154202
define double @cmp3(double %a, double %b, double %y, double %z) #0 {
@@ -160,20 +208,27 @@ entry:
160208
; CHECK: @cmp3
161209
; CHECK-NOT: fsel
162210
; CHECK: blr
211+
}
212+
213+
define double @cmp3_finite(double %a, double %b, double %y, double %z) #0 {
214+
entry:
215+
%cmp = fcmp ninf nnan oeq double %a, %b
216+
%y.z = select i1 %cmp, double %y, double %z
217+
ret double %y.z
163218

164-
; CHECK-FM: @cmp3
165-
; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
166-
; CHECK-FM: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
167-
; CHECK-FM: fneg [[REG3:[0-9]+]], [[REG]]
168-
; CHECK-FM: fsel 1, [[REG3]], [[REG2]], 4
169-
; CHECK-FM: blr
219+
; CHECK: @cmp3_finite
220+
; CHECK: fsub [[REG:[0-9]+]], 1, 2
221+
; CHECK: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
222+
; CHECK: fneg [[REG3:[0-9]+]], [[REG]]
223+
; CHECK: fsel 1, [[REG3]], [[REG2]], 4
224+
; CHECK: blr
170225

171-
; CHECK-FM-VSX: @cmp3
172-
; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
173-
; CHECK-FM-VSX: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
174-
; CHECK-FM-VSX: xsnegdp [[REG3:[0-9]+]], [[REG]]
175-
; CHECK-FM-VSX: fsel 1, [[REG3]], [[REG2]], 4
176-
; CHECK-FM-VSX: blr
226+
; CHECK-VSX: @cmp3_finite
227+
; CHECK-VSX: xssubdp [[REG:[0-9]+]], 1, 2
228+
; CHECK-VSX: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
229+
; CHECK-VSX: xsnegdp [[REG3:[0-9]+]], [[REG]]
230+
; CHECK-VSX: fsel 1, [[REG3]], [[REG2]], 4
231+
; CHECK-VSX: blr
177232
}
178233

179234
attributes #0 = { nounwind readnone }

0 commit comments

Comments
 (0)