[Headers][X86] VectorExprEvaluator::VisitCallExpr - allow MMX/SSE/AVX2/AVX512 shift by immediate intrinsics to be used in constexpr #154293
Description
Handle the vector shift by uniform immediate intrinsics inside VectorExprEvaluator::VisitCallExpr and add constexpr test coverage, similar to #152524
_mm_slli_pi16 _mm_srli_pi16 _mm_srai_pi16 _mm_slli_pi32 _mm_srli_pi32 _mm_srai_pi32 _mm_slli_si64 _mm_srli_si64 _mm*_slli_epi16 _mm*_srli_epi16 _mm*_srai_epi16 _mm*_slli_epi32 _mm*_srli_epi32 _mm*_srai_epi32 _mm*_slli_epi64 _mm*_srli_epi64 _mm*_srai_epi64 _mm*_mask_slli_epi16 _mm*_mask_srli_epi16 _mm*_mask_srai_epi16 _mm*_mask_slli_epi32 _mm*_mask_srli_epi32 _mm*_mask_srai_epi32 _mm*_mask_slli_epi64 _mm*_mask_srli_epi64 _mm*_mask_srai_epi64 _mm*_maskz_slli_epi16 _mm*_maskz_srli_epi16 _mm*_maskz_srai_epi16 _mm*_maskz_slli_epi32 _mm*_maskz_srli_epi32 _mm*_maskz_srai_epi32 _mm*_maskz_slli_epi64 _mm*_maskz_srli_epi64 _mm*_maskz_srai_epi64 - for 128/256/512 variants
The shift intrinsics have special case handling for out of bounds shift amounts, for logical shifts if the unsigned amount is greater than or equal to the element bitwidth then the result is 0. For arithmetic shifts, the shift amount is clamped to (bitwidth-1) to splat the sign bit.