- Notifications
You must be signed in to change notification settings - Fork 15.3k
Closed
Labels
llvm:instcombineCovers the InstCombine, InstSimplify and AggressiveInstCombine passesCovers the InstCombine, InstSimplify and AggressiveInstCombine passesmiscompilation
Milestone
Description
I tried this IR:
define <4 x i32> @src(i32 %arg) { %i = zext i32 %arg to i64 %i1 = shl i64 %i, 32 %i2 = or i64 %i1, 65 %i3 = zext i64 %i2 to i128 %i4 = shl i128 %i3, 64 %i5 = bitcast i128 %i4 to <4 x i32> ret <4 x i32> %i5 } define <4 x i32> @tgt(i32 %arg) { %i5 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 poison>, i32 %arg, i64 3 ret <4 x i32> %i5 }I expect src to be:
define <4 x i32> @src(i32 %arg) { %i5 = insertelement <4 x i32> <i32 0, i32 0, i32 65, i32 poison>, i32 %arg, i64 3 ret <4 x i32> %i5 }But I'm getting the same instructions as tgt.
Godbolt: https://llvm.godbolt.org/z/KnMEY4rTq
Alive2: https://alive2.llvm.org/ce/z/7FIJNi
From: rust-lang/rust#121996
Metadata
Metadata
Assignees
Labels
llvm:instcombineCovers the InstCombine, InstSimplify and AggressiveInstCombine passesCovers the InstCombine, InstSimplify and AggressiveInstCombine passesmiscompilation
Type
Projects
Status
Done