Search results

[RISCV] Propagate SDNode flags when combining <code>(fmul (fneg X), ...)</code>

backend:RISC-V

Status: Merged (completed).

llvm/llvm-projectnumber 169460

#169460 In llvm/llvm-project;

· by mshockwave was closed on Nov 25, 2025

[RISCV] Introduce a new tune feature string syntax and its parser

backend:RISC-V

tablegen

Status: Open (in progress).

llvm/llvm-projectnumber 168160

#168160 In llvm/llvm-project;

· mshockwave opened on Nov 15, 2025

[RISCV] Adopt SpacemitX60's scheduling model for <code>-mtune=generic</code>

backend:RISC-V

llvm:globalisel

Status: Open (in progress).

llvm/llvm-projectnumber 167008

#167008 In llvm/llvm-project;

· mshockwave opened on Nov 7, 2025

[MISched][NFC] Rename isUnbufferedGroup to isReservedGroup

llvm:codegen

mi-schedmachine instruction schedulermachine instruction scheduler

Status: Merged (completed).

llvm/llvm-projectnumber 166439

#166439 In llvm/llvm-project;

· by mshockwave was closed on Nov 5, 2025

[doc][RISCV] Add XSfvfexp* and XSfvfexpa* into RISCVUsage.rst

backend:RISC-V

Status: Merged (completed).

llvm/llvm-projectnumber 166198

#166198 In llvm/llvm-project;

· by mshockwave was closed on Nov 4, 2025

[clang][RISCV] Add C intrinsics for XSfvfexp* and XSfvfexpa*

backend:RISC-V

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:frontendLanguage frontend issues, e.g. anything involving "Sema"Language frontend issues, e.g. anything involving "Sema"

Status: Merged (completed).

llvm/llvm-projectnumber 165792

#165792 In llvm/llvm-project;

· by mshockwave was closed on Nov 3, 2025

[RISCV] Add LLVM IR intrinsics and codegen for XSfvfexp* and XSfvfexpa*

backend:RISC-V

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:driver'clang' and 'clang++' user-facing binaries. Not 'clang-cl''clang' and 'clang++' user-facing binaries. Not 'clang-cl'

llvm:ir

Status: Merged (completed).

llvm/llvm-projectnumber 164499

#164499 In llvm/llvm-project;

· by mshockwave was closed on Oct 24, 2025

[RISCV][MC] Introduce XSfvfexp* and XSfvfbfexpa* extensions and their MC supports

backend:RISC-V

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:driver'clang' and 'clang++' user-facing binaries. Not 'clang-cl''clang' and 'clang++' user-facing binaries. Not 'clang-cl'

Status: Merged (completed).

llvm/llvm-projectnumber 164349

#164349 In llvm/llvm-project;

· by mshockwave was closed on Oct 22, 2025

[RISCV][NO-MERGE] Discussions on passing tuning features from the Clang driver

backend:RISC-V

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:driver'clang' and 'clang++' user-facing binaries. Not 'clang-cl''clang' and 'clang++' user-facing binaries. Not 'clang-cl'

Status: Open (in progress).

llvm/llvm-projectnumber 162716

#162716 In llvm/llvm-project;

· mshockwave opened on Oct 9, 2025

[clang][Driver][RISCV] Rename <code>getRISCFeaturesFromMcpu</code>. NFCI

backend:RISC-V

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:driver'clang' and 'clang++' user-facing binaries. Not 'clang-cl''clang' and 'clang++' user-facing binaries. Not 'clang-cl'

Status: Merged (completed).

llvm/llvm-projectnumber 162545

#162545 In llvm/llvm-project;

· by mshockwave was closed on Oct 8, 2025

[RISCV] Toggle throttled FP64 feature in SiFive7 scheduling model with subtarget feature

backend:RISC-V

Status: Merged (completed).

llvm/llvm-projectnumber 162400

#162400 In llvm/llvm-project;

· by mshockwave was closed on Oct 10, 2025

[RISCV] Add a new subtarget feature for throttled FP64 vector performance

backend:RISC-V

Status: Merged (completed).

llvm/llvm-projectnumber 162399

#162399 In llvm/llvm-project;

· by mshockwave was closed on Oct 10, 2025