Search results

[RISCV] Wrong register allocation for vmerge.vvm

backend:RISC-V

llvm:regalloc

Status: Open.

Bug

#169905 In llvm/llvm-project;

· wangpc-pp opened on Nov 28, 2025

· 

LLVM 21.x Release

[PHIElimination] Declare MachineLoopInfo dependency for Legacy PM

backend:AMDGPU

llvm:codegen

llvm:regalloc

Status: Open (in progress).

llvm/llvm-projectnumber 169693

#169693 In llvm/llvm-project;

· PrasoonMishra opened on Nov 26, 2025

[RegAlloc] Fix the terminal rule check for interfere with DstReg

backend:AArch64

backend:AMDGPU

backend:Hexagon

backend:NVPTX

backend:PowerPC

backend:RISC-V

backend:WebAssembly

backend:X86

llvm:codegen

llvm:globalisel

llvm:regalloc

Status: Merged (completed).

llvm/llvm-projectnumber 168661

#168661 In llvm/llvm-project;

· by hstk30-hw was closed on Nov 23, 2025

[regalloc][LiveRegMatrix] Add validity check for LiveRegMatrix to prevent dangling pointers

llvm:codegen

llvm:regalloc

Status: Open (in progress).

llvm/llvm-projectnumber 168553

#168553 In llvm/llvm-project;

· vpykhtin opened on Nov 18, 2025

[CodeGen] Turn MCRegUnit into an enum class (NFC)

backend:AMDGPU

backend:X86

llvm:codegen

llvm:mcMachine (object) codeMachine (object) code

llvm:regalloc

Status: Merged (completed).

llvm/llvm-projectnumber 167943

#167943 In llvm/llvm-project;

· by s-barannikov was closed on Nov 16, 2025

[CodeGen] Use VirtRegOrUnit where appropriate (NFCI)

backend:AMDGPU

backend:ARM

llvm:codegen

llvm:regalloc

Status: Merged (completed).

llvm/llvm-projectnumber 167730

#167730 In llvm/llvm-project;

· by s-barannikov was closed on Nov 13, 2025

[RISCV64] liveness analysis

backend:RISC-V

llvm:regalloc

Status: Open (in progress).

llvm/llvm-projectnumber 167454

#167454 In llvm/llvm-project;

· hiraditya opened on Nov 11, 2025

Remove unused standard header inclusion: <iterator>, <utility>, <type_traits>

backend:AArch64

backend:AMDGPU

backend:ARM

backend:Hexagon

backend:NVPTX

backend:RISC-V

backend:SPIR-V

backend:SystemZ

backend:X86

debuginfo

llvm:adt

llvm:analysisIncludes value tracking, cost tables and constant foldingIncludes value tracking, cost tables and constant folding

llvm:binary-utilities

llvm:codegen

llvm:instcombineCovers the InstCombine, InstSimplify and AggressiveInstCombine passesCovers the InstCombine, InstSimplify and AggressiveInstCombine passes

llvm:ir

llvm:mcMachine (object) codeMachine (object) code

llvm:regalloc

llvm:support

llvm:transforms

Status: Closed (abandoned).

llvm/llvm-projectnumber 167318

#167318 In llvm/llvm-project;

· by serge-sans-paille was closed on Nov 11, 2025

AMDGPU: Relax shouldCoalesce to allow more register tuple widening

backend:AMDGPU

llvm:globalisel

llvm:regalloc

Status: Merged (completed).

llvm/llvm-projectnumber 166475

#166475 In llvm/llvm-project;

· by arsenm was closed on Nov 11, 2025

[Analysis, CodeGen] Use "= default" (NFC)

llvm:analysisIncludes value tracking, cost tables and constant foldingIncludes value tracking, cost tables and constant folding

llvm:codegen

llvm:regalloc

Status: Merged (completed).

llvm/llvm-projectnumber 166024

#166024 In llvm/llvm-project;

· by kazutakahirata was closed on Nov 2, 2025

CodeGen: Remove target hook for terminal rule

backend:AArch64

backend:AMDGPU

backend:ARM

backend:Hexagon

backend:NVPTX

backend:PowerPC

backend:RISC-V

backend:SystemZ

backend:WebAssembly

backend:X86

llvm:codegen

llvm:regalloc

Status: Merged (completed).

llvm/llvm-projectnumber 165962

#165962 In llvm/llvm-project;

· by arsenm was closed on Nov 12, 2025

[CodeGen] Add MachineRegisterClassInfo analysis pass

backend:AArch64

backend:AMDGPU

backend:ARM

backend:loongarch

backend:PowerPC

backend:RISC-V

backend:X86

llvm:codegen

llvm:regalloc

Status: Open (in progress).

llvm/llvm-projectnumber 164877

#164877 In llvm/llvm-project;

· linuxrocks123 opened on Oct 23, 2025