[RISCV] fix RISCVPushPopOptimizer pass

[daniilavdeev]

RISCVPushPopOptimizer pass didn't suggest that CFI instructions can be inserted between cm.pop and ret and couldn't apply optimization in these cases. The patch fix it and allows the pass to remove CFI instructions and combine cm.pop and ret into the one instruction: cm.popret or cm.popretz.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: None (dlav-sc)

Changes

RISCVPushPopOptimizer pass didn't suggest that CFI instructions can be inserted between cm.pop and ret and couldn't apply optimization in these cases. The patch fix it and allows the pass to remove CFI instructions and combine cm.pop and ret into the one instruction: cm.popret or cm.popretz.

---

Patch is 33.43 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/110813.diff

7 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp (+22-4)
• (modified) llvm/test/CodeGen/RISCV/callee-saved-gprs.ll (+8-24)
• (modified) llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll (+4-8)
• (modified) llvm/test/CodeGen/RISCV/push-pop-popret.ll (+44-180)
• (modified) llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll (+1-6)
• (modified) llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir (+4-22)
• (modified) llvm/test/CodeGen/RISCV/zcmp-with-float.ll (+2-10)

diff --git a/llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp index 098e5bb5328bb3..2b1d6c25891a1f 100644 --- a/llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp +++ b/llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp @@ -45,10 +45,25 @@ char RISCVPushPopOpt::ID = 0; INITIALIZE_PASS(RISCVPushPopOpt, "riscv-push-pop-opt", RISCV_PUSH_POP_OPT_NAME, false, false) +template <typename IterT> +static IterT nextNoDebugNoCFIInst(const IterT It, const IterT End) { + return std::find_if_not(std::next(It), End, [](const auto &Inst) { + return Inst.isDebugInstr() || Inst.isCFIInstruction() || + Inst.isPseudoProbe(); + }); +} + +static void eraseCFIInst(const MachineBasicBlock::iterator Begin, + const MachineBasicBlock::iterator End) { + for (auto &Inst : llvm::make_early_inc_range(llvm::make_range(Begin, End))) + if (Inst.isCFIInstruction()) + Inst.eraseFromParent(); +} + // Check if POP instruction was inserted into the MBB and return iterator to it. static MachineBasicBlock::iterator containsPop(MachineBasicBlock &MBB) { for (MachineBasicBlock::iterator MBBI = MBB.begin(); MBBI != MBB.end(); - MBBI = next_nodbg(MBBI, MBB.end())) + MBBI = nextNoDebugNoCFIInst(MBBI, MBB.end())) if (MBBI->getOpcode() == RISCV::CM_POP) return MBBI; @@ -76,6 +91,9 @@ bool RISCVPushPopOpt::usePopRet(MachineBasicBlock::iterator &MBBI, for (unsigned i = FirstNonDeclaredOp; i < MBBI->getNumOperands(); ++i) PopRetBuilder.add(MBBI->getOperand(i)); + // Remove CFI instructions, they are not needed for cm.popret and cm.popretz + eraseCFIInst(MBBI, NextI); + MBBI->eraseFromParent(); NextI->eraseFromParent(); return true; @@ -92,8 +110,8 @@ bool RISCVPushPopOpt::adjustRetVal(MachineBasicBlock::iterator &MBBI) { // Since POP instruction is in Epilogue no normal instructions will follow // after it. Therefore search only previous ones to find the return value. for (MachineBasicBlock::reverse_iterator I = - next_nodbg(MBBI.getReverse(), RE); - I != RE; I = next_nodbg(I, RE)) { + nextNoDebugNoCFIInst(MBBI.getReverse(), RE); + I != RE; I = nextNoDebugNoCFIInst(I, RE)) { MachineInstr &MI = *I; if (auto OperandPair = TII->isCopyInstrImpl(MI)) { Register DestReg = OperandPair->Destination->getReg(); @@ -138,7 +156,7 @@ bool RISCVPushPopOpt::runOnMachineFunction(MachineFunction &Fn) { bool Modified = false; for (auto &MBB : Fn) { MachineBasicBlock::iterator MBBI = containsPop(MBB); - MachineBasicBlock::iterator NextI = next_nodbg(MBBI, MBB.end()); + MachineBasicBlock::iterator NextI = nextNoDebugNoCFIInst(MBBI, MBB.end()); if (MBBI != MBB.end() && NextI != MBB.end() && NextI->getOpcode() == RISCV::PseudoRET) Modified |= usePopRet(MBBI, NextI, adjustRetVal(MBBI)); diff --git a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll index 2a26602de9e1e7..528e52bad8ef1a 100644 --- a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll +++ b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll @@ -432,8 +432,7 @@ define void @callee() nounwind { ; RV32IZCMP-NEXT: sw a0, %lo(var+4)(t0) ; RV32IZCMP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload ; RV32IZCMP-NEXT: sw a0, %lo(var)(t0) -; RV32IZCMP-NEXT: cm.pop {ra, s0-s11}, 96 -; RV32IZCMP-NEXT: ret +; RV32IZCMP-NEXT: cm.popret {ra, s0-s11}, 96 ; ; RV32IZCMP-WITH-FP-LABEL: callee: ; RV32IZCMP-WITH-FP: # %bb.0: @@ -942,8 +941,7 @@ define void @callee() nounwind { ; RV64IZCMP-NEXT: sw a0, %lo(var+4)(t0) ; RV64IZCMP-NEXT: ld a0, 40(sp) # 8-byte Folded Reload ; RV64IZCMP-NEXT: sw a0, %lo(var)(t0) -; RV64IZCMP-NEXT: cm.pop {ra, s0-s11}, 160 -; RV64IZCMP-NEXT: ret +; RV64IZCMP-NEXT: cm.popret {ra, s0-s11}, 160 ; ; RV64IZCMP-WITH-FP-LABEL: callee: ; RV64IZCMP-WITH-FP: # %bb.0: @@ -1613,8 +1611,7 @@ define void @caller() nounwind { ; RV32IZCMP-NEXT: lw a0, 92(sp) # 4-byte Folded Reload ; RV32IZCMP-NEXT: sw a0, %lo(var)(s0) ; RV32IZCMP-NEXT: addi sp, sp, 48 -; RV32IZCMP-NEXT: cm.pop {ra, s0-s11}, 112 -; RV32IZCMP-NEXT: ret +; RV32IZCMP-NEXT: cm.popret {ra, s0-s11}, 112 ; ; RV32IZCMP-WITH-FP-LABEL: caller: ; RV32IZCMP-WITH-FP: # %bb.0: @@ -2309,8 +2306,7 @@ define void @caller() nounwind { ; RV64IZCMP-NEXT: ld a0, 168(sp) # 8-byte Folded Reload ; RV64IZCMP-NEXT: sw a0, %lo(var)(s0) ; RV64IZCMP-NEXT: addi sp, sp, 128 -; RV64IZCMP-NEXT: cm.pop {ra, s0-s11}, 160 -; RV64IZCMP-NEXT: ret +; RV64IZCMP-NEXT: cm.popret {ra, s0-s11}, 160 ; ; RV64IZCMP-WITH-FP-LABEL: caller: ; RV64IZCMP-WITH-FP: # %bb.0: @@ -2521,10 +2517,7 @@ define void @foo() { ; RV32IZCMP-NEXT: #APP ; RV32IZCMP-NEXT: li s4, 0 ; RV32IZCMP-NEXT: #NO_APP -; RV32IZCMP-NEXT: cm.pop {ra, s0-s4}, 32 -; RV32IZCMP-NEXT: .cfi_def_cfa_offset 0 -; RV32IZCMP-NEXT: .cfi_restore s4 -; RV32IZCMP-NEXT: ret +; RV32IZCMP-NEXT: cm.popret {ra, s0-s4}, 32 ; ; RV32IZCMP-WITH-FP-LABEL: foo: ; RV32IZCMP-WITH-FP: # %bb.0: # %entry @@ -2606,10 +2599,7 @@ define void @foo() { ; RV64IZCMP-NEXT: #APP ; RV64IZCMP-NEXT: li s4, 0 ; RV64IZCMP-NEXT: #NO_APP -; RV64IZCMP-NEXT: cm.pop {ra, s0-s4}, 48 -; RV64IZCMP-NEXT: .cfi_def_cfa_offset 0 -; RV64IZCMP-NEXT: .cfi_restore s4 -; RV64IZCMP-NEXT: ret +; RV64IZCMP-NEXT: cm.popret {ra, s0-s4}, 48 ; ; RV64IZCMP-WITH-FP-LABEL: foo: ; RV64IZCMP-WITH-FP: # %bb.0: # %entry @@ -2697,10 +2687,7 @@ define void @bar() { ; RV32IZCMP-NEXT: #APP ; RV32IZCMP-NEXT: li s11, 0 ; RV32IZCMP-NEXT: #NO_APP -; RV32IZCMP-NEXT: cm.pop {ra, s0-s11}, 64 -; RV32IZCMP-NEXT: .cfi_def_cfa_offset 0 -; RV32IZCMP-NEXT: .cfi_restore s11 -; RV32IZCMP-NEXT: ret +; RV32IZCMP-NEXT: cm.popret {ra, s0-s11}, 64 ; ; RV32IZCMP-WITH-FP-LABEL: bar: ; RV32IZCMP-WITH-FP: # %bb.0: # %entry @@ -2782,10 +2769,7 @@ define void @bar() { ; RV64IZCMP-NEXT: #APP ; RV64IZCMP-NEXT: li s11, 0 ; RV64IZCMP-NEXT: #NO_APP -; RV64IZCMP-NEXT: cm.pop {ra, s0-s11}, 112 -; RV64IZCMP-NEXT: .cfi_def_cfa_offset 0 -; RV64IZCMP-NEXT: .cfi_restore s11 -; RV64IZCMP-NEXT: ret +; RV64IZCMP-NEXT: cm.popret {ra, s0-s11}, 112 ; ; RV64IZCMP-WITH-FP-LABEL: bar: ; RV64IZCMP-WITH-FP: # %bb.0: # %entry diff --git a/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll b/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll index 647c27752b1ed6..2103c3e60b591c 100644 --- a/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll +++ b/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll @@ -43,8 +43,7 @@ define i32 @zcmp_mv(i32 %num, i32 %f) nounwind { ; CHECK32ZCMP-NEXT: cm.mva01s s1, s0 ; CHECK32ZCMP-NEXT: call func ; CHECK32ZCMP-NEXT: add a0, s2, s0 -; CHECK32ZCMP-NEXT: cm.pop {ra, s0-s2}, 16 -; CHECK32ZCMP-NEXT: ret +; CHECK32ZCMP-NEXT: cm.popret {ra, s0-s2}, 16 ; ; CHECK64I-LABEL: zcmp_mv: ; CHECK64I: # %bb.0: @@ -77,8 +76,7 @@ define i32 @zcmp_mv(i32 %num, i32 %f) nounwind { ; CHECK64ZCMP-NEXT: cm.mva01s s1, s0 ; CHECK64ZCMP-NEXT: call func ; CHECK64ZCMP-NEXT: addw a0, s2, s0 -; CHECK64ZCMP-NEXT: cm.pop {ra, s0-s2}, 32 -; CHECK64ZCMP-NEXT: ret +; CHECK64ZCMP-NEXT: cm.popret {ra, s0-s2}, 32 %call = call i32 @func(i32 %num, i32 %f) %call1 = call i32 @func(i32 %num, i32 %f) %res = add i32 %call, %f @@ -121,8 +119,7 @@ define i32 @not_zcmp_mv(i32 %num, i32 %f) nounwind { ; CHECK32ZCMP-NEXT: li a0, 1 ; CHECK32ZCMP-NEXT: mv a1, s0 ; CHECK32ZCMP-NEXT: call func -; CHECK32ZCMP-NEXT: cm.pop {ra, s0-s1}, 16 -; CHECK32ZCMP-NEXT: ret +; CHECK32ZCMP-NEXT: cm.popret {ra, s0-s1}, 16 ; ; CHECK64I-LABEL: not_zcmp_mv: ; CHECK64I: # %bb.0: @@ -159,8 +156,7 @@ define i32 @not_zcmp_mv(i32 %num, i32 %f) nounwind { ; CHECK64ZCMP-NEXT: li a0, 1 ; CHECK64ZCMP-NEXT: mv a1, s0 ; CHECK64ZCMP-NEXT: call func -; CHECK64ZCMP-NEXT: cm.pop {ra, s0-s1}, 32 -; CHECK64ZCMP-NEXT: ret +; CHECK64ZCMP-NEXT: cm.popret {ra, s0-s1}, 32 %call = call i32 @foo(i32 %num) %call1 = call i32 @foo(i32 %f) %tmp = call i32 @foo(i32 %call) diff --git a/llvm/test/CodeGen/RISCV/push-pop-popret.ll b/llvm/test/CodeGen/RISCV/push-pop-popret.ll index c856d9e336b34e..7827d269879515 100644 --- a/llvm/test/CodeGen/RISCV/push-pop-popret.ll +++ b/llvm/test/CodeGen/RISCV/push-pop-popret.ll @@ -25,13 +25,9 @@ define i32 @foo() { ; RV32IZCMP-NEXT: .cfi_offset ra, -4 ; RV32IZCMP-NEXT: mv a0, sp ; RV32IZCMP-NEXT: call test -; RV32IZCMP-NEXT: li a0, 0 ; RV32IZCMP-NEXT: addi sp, sp, 464 ; RV32IZCMP-NEXT: .cfi_def_cfa_offset 64 -; RV32IZCMP-NEXT: cm.pop {ra}, 64 -; RV32IZCMP-NEXT: .cfi_def_cfa_offset 0 -; RV32IZCMP-NEXT: .cfi_restore ra -; RV32IZCMP-NEXT: ret +; RV32IZCMP-NEXT: cm.popretz {ra}, 64 ; ; RV64IZCMP-LABEL: foo: ; RV64IZCMP: # %bb.0: @@ -41,13 +37,9 @@ define i32 @foo() { ; RV64IZCMP-NEXT: .cfi_offset ra, -8 ; RV64IZCMP-NEXT: mv a0, sp ; RV64IZCMP-NEXT: call test -; RV64IZCMP-NEXT: li a0, 0 ; RV64IZCMP-NEXT: addi sp, sp, 464 ; RV64IZCMP-NEXT: .cfi_def_cfa_offset 64 -; RV64IZCMP-NEXT: cm.pop {ra}, 64 -; RV64IZCMP-NEXT: .cfi_def_cfa_offset 0 -; RV64IZCMP-NEXT: .cfi_restore ra -; RV64IZCMP-NEXT: ret +; RV64IZCMP-NEXT: cm.popretz {ra}, 64 ; ; RV32IZCMP-SR-LABEL: foo: ; RV32IZCMP-SR: # %bb.0: @@ -57,13 +49,9 @@ define i32 @foo() { ; RV32IZCMP-SR-NEXT: .cfi_offset ra, -4 ; RV32IZCMP-SR-NEXT: mv a0, sp ; RV32IZCMP-SR-NEXT: call test -; RV32IZCMP-SR-NEXT: li a0, 0 ; RV32IZCMP-SR-NEXT: addi sp, sp, 464 ; RV32IZCMP-SR-NEXT: .cfi_def_cfa_offset 64 -; RV32IZCMP-SR-NEXT: cm.pop {ra}, 64 -; RV32IZCMP-SR-NEXT: .cfi_def_cfa_offset 0 -; RV32IZCMP-SR-NEXT: .cfi_restore ra -; RV32IZCMP-SR-NEXT: ret +; RV32IZCMP-SR-NEXT: cm.popretz {ra}, 64 ; ; RV64IZCMP-SR-LABEL: foo: ; RV64IZCMP-SR: # %bb.0: @@ -73,13 +61,9 @@ define i32 @foo() { ; RV64IZCMP-SR-NEXT: .cfi_offset ra, -8 ; RV64IZCMP-SR-NEXT: mv a0, sp ; RV64IZCMP-SR-NEXT: call test -; RV64IZCMP-SR-NEXT: li a0, 0 ; RV64IZCMP-SR-NEXT: addi sp, sp, 464 ; RV64IZCMP-SR-NEXT: .cfi_def_cfa_offset 64 -; RV64IZCMP-SR-NEXT: cm.pop {ra}, 64 -; RV64IZCMP-SR-NEXT: .cfi_def_cfa_offset 0 -; RV64IZCMP-SR-NEXT: .cfi_restore ra -; RV64IZCMP-SR-NEXT: ret +; RV64IZCMP-SR-NEXT: cm.popretz {ra}, 64 ; ; RV32I-LABEL: foo: ; RV32I: # %bb.0: @@ -130,14 +114,9 @@ define i32 @pushpopret0(i32 signext %size){ ; RV32IZCMP-NEXT: sub a0, sp, a0 ; RV32IZCMP-NEXT: mv sp, a0 ; RV32IZCMP-NEXT: call callee_void -; RV32IZCMP-NEXT: li a0, 0 ; RV32IZCMP-NEXT: addi sp, s0, -16 ; RV32IZCMP-NEXT: .cfi_def_cfa sp, 16 -; RV32IZCMP-NEXT: cm.pop {ra, s0}, 16 -; RV32IZCMP-NEXT: .cfi_def_cfa_offset 0 -; RV32IZCMP-NEXT: .cfi_restore ra -; RV32IZCMP-NEXT: .cfi_restore s0 -; RV32IZCMP-NEXT: ret +; RV32IZCMP-NEXT: cm.popretz {ra, s0}, 16 ; ; RV64IZCMP-LABEL: pushpopret0: ; RV64IZCMP: # %bb.0: # %entry @@ -154,14 +133,9 @@ define i32 @pushpopret0(i32 signext %size){ ; RV64IZCMP-NEXT: sub a0, sp, a0 ; RV64IZCMP-NEXT: mv sp, a0 ; RV64IZCMP-NEXT: call callee_void -; RV64IZCMP-NEXT: li a0, 0 ; RV64IZCMP-NEXT: addi sp, s0, -16 ; RV64IZCMP-NEXT: .cfi_def_cfa sp, 16 -; RV64IZCMP-NEXT: cm.pop {ra, s0}, 16 -; RV64IZCMP-NEXT: .cfi_def_cfa_offset 0 -; RV64IZCMP-NEXT: .cfi_restore ra -; RV64IZCMP-NEXT: .cfi_restore s0 -; RV64IZCMP-NEXT: ret +; RV64IZCMP-NEXT: cm.popretz {ra, s0}, 16 ; ; RV32IZCMP-SR-LABEL: pushpopret0: ; RV32IZCMP-SR: # %bb.0: # %entry @@ -176,14 +150,9 @@ define i32 @pushpopret0(i32 signext %size){ ; RV32IZCMP-SR-NEXT: sub a0, sp, a0 ; RV32IZCMP-SR-NEXT: mv sp, a0 ; RV32IZCMP-SR-NEXT: call callee_void -; RV32IZCMP-SR-NEXT: li a0, 0 ; RV32IZCMP-SR-NEXT: addi sp, s0, -16 ; RV32IZCMP-SR-NEXT: .cfi_def_cfa sp, 16 -; RV32IZCMP-SR-NEXT: cm.pop {ra, s0}, 16 -; RV32IZCMP-SR-NEXT: .cfi_def_cfa_offset 0 -; RV32IZCMP-SR-NEXT: .cfi_restore ra -; RV32IZCMP-SR-NEXT: .cfi_restore s0 -; RV32IZCMP-SR-NEXT: ret +; RV32IZCMP-SR-NEXT: cm.popretz {ra, s0}, 16 ; ; RV64IZCMP-SR-LABEL: pushpopret0: ; RV64IZCMP-SR: # %bb.0: # %entry @@ -200,14 +169,9 @@ define i32 @pushpopret0(i32 signext %size){ ; RV64IZCMP-SR-NEXT: sub a0, sp, a0 ; RV64IZCMP-SR-NEXT: mv sp, a0 ; RV64IZCMP-SR-NEXT: call callee_void -; RV64IZCMP-SR-NEXT: li a0, 0 ; RV64IZCMP-SR-NEXT: addi sp, s0, -16 ; RV64IZCMP-SR-NEXT: .cfi_def_cfa sp, 16 -; RV64IZCMP-SR-NEXT: cm.pop {ra, s0}, 16 -; RV64IZCMP-SR-NEXT: .cfi_def_cfa_offset 0 -; RV64IZCMP-SR-NEXT: .cfi_restore ra -; RV64IZCMP-SR-NEXT: .cfi_restore s0 -; RV64IZCMP-SR-NEXT: ret +; RV64IZCMP-SR-NEXT: cm.popretz {ra, s0}, 16 ; ; RV32I-LABEL: pushpopret0: ; RV32I: # %bb.0: # %entry @@ -285,11 +249,7 @@ define i32 @pushpopret1(i32 signext %size) { ; RV32IZCMP-NEXT: li a0, 1 ; RV32IZCMP-NEXT: addi sp, s0, -16 ; RV32IZCMP-NEXT: .cfi_def_cfa sp, 16 -; RV32IZCMP-NEXT: cm.pop {ra, s0}, 16 -; RV32IZCMP-NEXT: .cfi_def_cfa_offset 0 -; RV32IZCMP-NEXT: .cfi_restore ra -; RV32IZCMP-NEXT: .cfi_restore s0 -; RV32IZCMP-NEXT: ret +; RV32IZCMP-NEXT: cm.popret {ra, s0}, 16 ; ; RV64IZCMP-LABEL: pushpopret1: ; RV64IZCMP: # %bb.0: # %entry @@ -309,11 +269,7 @@ define i32 @pushpopret1(i32 signext %size) { ; RV64IZCMP-NEXT: li a0, 1 ; RV64IZCMP-NEXT: addi sp, s0, -16 ; RV64IZCMP-NEXT: .cfi_def_cfa sp, 16 -; RV64IZCMP-NEXT: cm.pop {ra, s0}, 16 -; RV64IZCMP-NEXT: .cfi_def_cfa_offset 0 -; RV64IZCMP-NEXT: .cfi_restore ra -; RV64IZCMP-NEXT: .cfi_restore s0 -; RV64IZCMP-NEXT: ret +; RV64IZCMP-NEXT: cm.popret {ra, s0}, 16 ; ; RV32IZCMP-SR-LABEL: pushpopret1: ; RV32IZCMP-SR: # %bb.0: # %entry @@ -331,11 +287,7 @@ define i32 @pushpopret1(i32 signext %size) { ; RV32IZCMP-SR-NEXT: li a0, 1 ; RV32IZCMP-SR-NEXT: addi sp, s0, -16 ; RV32IZCMP-SR-NEXT: .cfi_def_cfa sp, 16 -; RV32IZCMP-SR-NEXT: cm.pop {ra, s0}, 16 -; RV32IZCMP-SR-NEXT: .cfi_def_cfa_offset 0 -; RV32IZCMP-SR-NEXT: .cfi_restore ra -; RV32IZCMP-SR-NEXT: .cfi_restore s0 -; RV32IZCMP-SR-NEXT: ret +; RV32IZCMP-SR-NEXT: cm.popret {ra, s0}, 16 ; ; RV64IZCMP-SR-LABEL: pushpopret1: ; RV64IZCMP-SR: # %bb.0: # %entry @@ -355,11 +307,7 @@ define i32 @pushpopret1(i32 signext %size) { ; RV64IZCMP-SR-NEXT: li a0, 1 ; RV64IZCMP-SR-NEXT: addi sp, s0, -16 ; RV64IZCMP-SR-NEXT: .cfi_def_cfa sp, 16 -; RV64IZCMP-SR-NEXT: cm.pop {ra, s0}, 16 -; RV64IZCMP-SR-NEXT: .cfi_def_cfa_offset 0 -; RV64IZCMP-SR-NEXT: .cfi_restore ra -; RV64IZCMP-SR-NEXT: .cfi_restore s0 -; RV64IZCMP-SR-NEXT: ret +; RV64IZCMP-SR-NEXT: cm.popret {ra, s0}, 16 ; ; RV32I-LABEL: pushpopret1: ; RV32I: # %bb.0: # %entry @@ -437,11 +385,7 @@ define i32 @pushpopretneg1(i32 signext %size) { ; RV32IZCMP-NEXT: li a0, -1 ; RV32IZCMP-NEXT: addi sp, s0, -16 ; RV32IZCMP-NEXT: .cfi_def_cfa sp, 16 -; RV32IZCMP-NEXT: cm.pop {ra, s0}, 16 -; RV32IZCMP-NEXT: .cfi_def_cfa_offset 0 -; RV32IZCMP-NEXT: .cfi_restore ra -; RV32IZCMP-NEXT: .cfi_restore s0 -; RV32IZCMP-NEXT: ret +; RV32IZCMP-NEXT: cm.popret {ra, s0}, 16 ; ; RV64IZCMP-LABEL: pushpopretneg1: ; RV64IZCMP: # %bb.0: # %entry @@ -461,11 +405,7 @@ define i32 @pushpopretneg1(i32 signext %size) { ; RV64IZCMP-NEXT: li a0, -1 ; RV64IZCMP-NEXT: addi sp, s0, -16 ; RV64IZCMP-NEXT: .cfi_def_cfa sp, 16 -; RV64IZCMP-NEXT: cm.pop {ra, s0}, 16 -; RV64IZCMP-NEXT: .cfi_def_cfa_offset 0 -; RV64IZCMP-NEXT: .cfi_restore ra -; RV64IZCMP-NEXT: .cfi_restore s0 -; RV64IZCMP-NEXT: ret +; RV64IZCMP-NEXT: cm.popret {ra, s0}, 16 ; ; RV32IZCMP-SR-LABEL: pushpopretneg1: ; RV32IZCMP-SR: # %bb.0: # %entry @@ -483,11 +423,7 @@ define i32 @pushpopretneg1(i32 signext %size) { ; RV32IZCMP-SR-NEXT: li a0, -1 ; RV32IZCMP-SR-NEXT: addi sp, s0, -16 ; RV32IZCMP-SR-NEXT: .cfi_def_cfa sp, 16 -; RV32IZCMP-SR-NEXT: cm.pop {ra, s0}, 16 -; RV32IZCMP-SR-NEXT: .cfi_def_cfa_offset 0 -; RV32IZCMP-SR-NEXT: .cfi_restore ra -; RV32IZCMP-SR-NEXT: .cfi_restore s0 -; RV32IZCMP-SR-NEXT: ret +; RV32IZCMP-SR-NEXT: cm.popret {ra, s0}, 16 ; ; RV64IZCMP-SR-LABEL: pushpopretneg1: ; RV64IZCMP-SR: # %bb.0: # %entry @@ -507,11 +443,7 @@ define i32 @pushpopretneg1(i32 signext %size) { ; RV64IZCMP-SR-NEXT: li a0, -1 ; RV64IZCMP-SR-NEXT: addi sp, s0, -16 ; RV64IZCMP-SR-NEXT: .cfi_def_cfa sp, 16 -; RV64IZCMP-SR-NEXT: cm.pop {ra, s0}, 16 -; RV64IZCMP-SR-NEXT: .cfi_def_cfa_offset 0 -; RV64IZCMP-SR-NEXT: .cfi_restore ra -; RV64IZCMP-SR-NEXT: .cfi_restore s0 -; RV64IZCMP-SR-NEXT: ret +; RV64IZCMP-SR-NEXT: cm.popret {ra, s0}, 16 ; ; RV32I-LABEL: pushpopretneg1: ; RV32I: # %bb.0: # %entry @@ -589,11 +521,7 @@ define i32 @pushpopret2(i32 signext %size) { ; RV32IZCMP-NEXT: li a0, 2 ; RV32IZCMP-NEXT: addi sp, s0, -16 ; RV32IZCMP-NEXT: .cfi_def_cfa sp, 16 -; RV32IZCMP-NEXT: cm.pop {ra, s0}, 16 -; RV32IZCMP-NEXT: .cfi_def_cfa_offset 0 -; RV32IZCMP-NEXT: .cfi_restore ra -; RV32IZCMP-NEXT: .cfi_restore s0 -; RV32IZCMP-NEXT: ret +; RV32IZCMP-NEXT: cm.popret {ra, s0}, 16 ; ; RV64IZCMP-LABEL: pushpopret2: ; RV64IZCMP: # %bb.0: # %entry @@ -613,11 +541,7 @@ define i32 @pushpopret2(i32 signext %size) { ; RV64IZCMP-NEXT: li a0, 2 ; RV64IZCMP-NEXT: addi sp, s0, -16 ; RV64IZCMP-NEXT: .cfi_def_cfa sp, 16 -; RV64IZCMP-NEXT: cm.pop {ra, s0}, 16 -; RV64IZCMP-NEXT: .cfi_def_cfa_offset 0 -; RV64IZCMP-NEXT: .cfi_restore ra -; RV64IZCMP-NEXT: .cfi_restore s0 -; RV64IZCMP-NEXT: ret +; RV64IZCMP-NEXT: cm.popret {ra, s0}, 16 ; ; RV32IZCMP-SR-LABEL: pushpopret2: ; RV32IZCMP-SR: # %bb.0: # %entry @@ -635,11 +559,7 @@ define i32 @pushpopret2(i32 signext %size) { ; RV32IZCMP-SR-NEXT: li a0, 2 ; RV32IZCMP-SR-NEXT: addi sp, s0, -16 ; RV32IZCMP-SR-NEXT: .cfi_def_cfa sp, 16 -; RV32IZCMP-SR-NEXT: cm.pop {ra, s0}, 16 -; RV32IZCMP-SR-NEXT: .cfi_def_cfa_offset 0 -; RV32IZCMP-SR-NEXT: .cfi_restore ra -; RV32IZCMP-SR-NEXT: .cfi_restore s0 -; RV32IZCMP-SR-NEXT: ret +; RV32IZCMP-SR-NEXT: cm.popret {ra, s0}, 16 ; ; RV64IZCMP-SR-LABEL: pushpopret2: ; RV64IZCMP-SR: # %bb.0: # %entry @@ -659,11 +579,7 @@ define i32 @pushpopret2(i32 signext %size) { ; RV64IZCMP-SR-NEXT: li a0, 2 ; RV64IZCMP-SR-NEXT: addi sp, s0, -16 ; RV64IZCMP-SR-NEXT: .cfi_def_cfa sp, 16 -; RV64IZCMP-SR-NEXT: cm.pop {ra, s0}, 16 -; RV64IZCMP-SR-NEXT: .cfi_def_cfa_offset 0 -; RV64IZCMP-SR-NEXT: .cfi_restore ra -; RV64IZCMP-SR-NEXT: .cfi_restore s0 -; RV64IZCMP-SR-NEXT: ret +; RV64IZCMP-SR-NEXT: cm.popret {ra, s0}, 16 ; ; RV32I-LABEL: pushpopret2: ; RV32I: # %bb.0: # %entry @@ -1381,8 +1297,7 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind { ; RV32IZCMP-NEXT: sw t0, %lo(var0+8)(a0) ; RV32IZCMP-NEXT: sw a7, %lo(var0+4)(a0) ; RV32IZCMP-NEXT: sw a6, %lo(var0)(a0) -; RV32IZCMP-NEXT: cm.pop {ra, s0-s4}, 32 -; RV32IZCMP-NEXT: ret +; RV32IZCMP-NEXT: cm.popret {ra, s0-s4}, 32 ; ; RV64IZCMP-LABEL: many_args: ; RV64IZCMP: # %bb.0: # %entry @@ -1425,8 +1340,7 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind { ; RV64IZCMP-NEXT: sw t0, %lo(var0+8)(a0) ; RV64IZCMP-NEXT: sw a7, %lo(var0+4)(a0) ; RV64IZCMP-NEXT: sw a6, %lo(var0)(a0) -; RV64IZCMP-NEXT: cm.pop {ra, s0-s4}, 48 -; RV64IZCMP-NEXT: ret +; RV64IZCMP-NEXT: cm.popret {ra, s0-s4}, 48 ; ; RV32IZCMP-SR-LABEL: many_args: ; RV32IZCMP-SR: # %bb.0: # %entry @@ -1469,8 +1383,7 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind { ; RV32IZCMP-SR-NEXT: sw t0, %lo(var0+8)(a0) ; RV32IZCMP-SR-NEXT: sw a7, %lo(var0+4)(a0) ; RV32IZCMP-SR-NEXT: sw a6, %lo(var0)(a0) -; RV32IZCMP-SR-NEXT: cm.pop {ra, s0-s4}, 32 -; RV32IZCMP-SR-NEXT: ret +; RV32IZCMP-SR-NEXT: cm.popret {ra, s0-s4}, 32 ; ; RV64IZCMP-SR-LABEL: many_args: ; RV64IZCMP-SR: # %bb.0: # %entry @@ -1513,8 +1426,7 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind { ; RV64IZCMP-SR-NEXT: sw t0, %lo(var0+8)(a0) ; RV64IZCMP-SR-NEXT... [truncated] 

[daniilavdeev]

@topperc @michaelmaitland FYI

[daniilavdeev]

@topperc @michaelmaitland, could you take another look, please?

[topperc]

LGTM

[daniilavdeev]

Deprecated

I've changed the logic of #110810, so this patch is not needed anymore.