[AMDGPU] Add liverange split instructions into BB Prolog

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -9709,6 +9709,30 @@ unsigned SIInstrInfo::getLiveRangeSplitOpcode(Register SrcReg,
  return AMDGPU::COPY;
 }
 
+bool SIInstrInfo::canAddToBBProlog(const MachineInstr &MI) const {
+ uint16_t Opcode = MI.getOpcode();
+ // Check if it is SGPR spill or wwm-register spill Opcode.
+ if (isSGPRSpill(Opcode) || isWWMRegSpillOpcode(Opcode))
+ return true;
+
+ const MachineFunction *MF = MI.getMF();
+ const MachineRegisterInfo &MRI = MF->getRegInfo();
+ const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
+
+ // See if this is Liverange split instruction inserted for SGPR or
+ // wwm-register. The implicit def inserted for wwm-registers should also be
+ // included as they can appear at the bb begin.
+ bool IsLRSplitInst = MI.getFlag(MachineInstr::LRSplit);
+ if (!IsLRSplitInst && Opcode != AMDGPU::IMPLICIT_DEF)
+ return false;
+
+ Register Reg = MI.getOperand(0).getReg();
+ if (RI.isSGPRClass(RI.getRegClassForReg(MRI, Reg)))
+ return IsLRSplitInst;
+
+ return MFI->isWWMReg(Reg);
+}
+
 bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI,
  Register Reg) const {
  // We need to handle instructions which may be inserted during register
@@ -9717,20 +9741,16 @@ bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI,
  // needed by the prolog. However, the insertions for scalar registers can
  // always be placed at the BB top as they are independent of the exec mask
  // value.
- const MachineFunction *MF = MI.getParent()->getParent();
  bool IsNullOrVectorRegister = true;
  if (Reg) {
+ const MachineFunction *MF = MI.getMF();
  const MachineRegisterInfo &MRI = MF->getRegInfo();
  IsNullOrVectorRegister = !RI.isSGPRClass(RI.getRegClassForReg(MRI, Reg));
  }
 
- uint16_t Opcode = MI.getOpcode();
- const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
  return IsNullOrVectorRegister &&
- (isSGPRSpill(Opcode) || isWWMRegSpillOpcode(Opcode) ||
- (Opcode == AMDGPU::IMPLICIT_DEF &&
- MFI->isWWMReg(MI.getOperand(0).getReg())) ||
- (!MI.isTerminator() && Opcode != AMDGPU::COPY &&
+ (canAddToBBProlog(MI) ||
+ (!MI.isTerminator() && MI.getOpcode() != AMDGPU::COPY &&
  MI.modifiesRegister(AMDGPU::EXEC, &RI)));
 }
 

llvm/lib/Target/AMDGPU/SIInstrInfo.h

@@ -1561,6 +1561,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
  bool isBasicBlockPrologue(const MachineInstr &MI,
  Register Reg = Register()) const override;
 
+ bool canAddToBBProlog(const MachineInstr &MI) const;
+
  MachineInstr *createPHIDestinationCopy(MachineBasicBlock &MBB,
  MachineBasicBlock::iterator InsPt,
  const DebugLoc &DL, Register Src,