[TargetInstrInfo] Add target hook for InstrSchedModel latency. [NFCI]

[kerbowa]

These hooks already exist when using instruction itineraries for latency
info, this patch adds them for the newer TargetSchedModel.

Allows targets to dynamically set latency values in the DAG builder.
This is useful in multi-pass schedulers like in the AMDGUP backend where
we may want to schedule a region multiple times with a different machine
model or tweaked latencies for a specific instruction type.

[kerbowa]

• [AMDGPU] Dynamically set load latency in the scheduler #128930
• [TargetInstrInfo] Add target hook for InstrSchedModel latency. [NFCI] #128925 👈 (View in Graphite)
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git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/include/llvm/CodeGen/TargetInstrInfo.h llvm/include/llvm/CodeGen/TargetSchedule.h llvm/lib/CodeGen/TargetInstrInfo.cpp llvm/lib/CodeGen/TargetSchedule.cpp

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diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp index 70c9d86e2..874f28af3 100644 --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -1842,11 +1842,9 @@ TargetInstrInfo::getInstrLatency(const TargetSchedModel &TargetSchedModel, return std::nullopt; } -std::optional<unsigned> TargetInstrInfo::getOperandLatency(const TargetSchedModel &SchedModel, - const MachineInstr *DefMI, - unsigned DefOperIdx, - const MachineInstr *UseMI, - unsigned UseOperIdx) const { +std::optional<unsigned> TargetInstrInfo::getOperandLatency( + const TargetSchedModel &SchedModel, const MachineInstr *DefMI, + unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const { // Only handle the TargetSchedModel-based computation here. If no // instruction scheduling model is available, defer to the caller. if (!SchedModel.hasInstrSchedModel()) @@ -1866,9 +1864,11 @@ std::optional<unsigned> TargetInstrInfo::getOperandLatency(const TargetSchedMode if (DefIdx < SCDesc->NumWriteLatencyEntries) { // Lookup the definition's write latency in SubtargetInfo. const TargetSubtargetInfo *STI = SchedModel.getSubtargetInfo(); - const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc, DefIdx); + const MCWriteLatencyEntry *WLEntry = + STI->getWriteLatencyEntry(SCDesc, DefIdx); unsigned WriteID = WLEntry->WriteResourceID; - unsigned Latency = WLEntry->Cycles >= 0 ? static_cast<unsigned>(WLEntry->Cycles) : 1000u; + unsigned Latency = + WLEntry->Cycles >= 0 ? static_cast<unsigned>(WLEntry->Cycles) : 1000u; if (!UseMI) return Latency; @@ -1884,7 +1884,8 @@ std::optional<unsigned> TargetInstrInfo::getOperandLatency(const TargetSchedMode ++UseIdx; } int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID); - if (Advance > 0 && static_cast<unsigned>(Advance) > Latency) // unsigned wrap + if (Advance > 0 && + static_cast<unsigned>(Advance) > Latency) // unsigned wrap return 0; return Latency - Advance; } @@ -1896,8 +1897,7 @@ std::optional<unsigned> TargetInstrInfo::getOperandLatency(const TargetSchedMode !DefMI->getDesc().operands()[DefOperIdx].isOptionalDef() && SchedModel.getMCSchedModel()->isComplete()) { errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " - << *DefMI - << " (Try with MCSchedModel.CompleteModel set to false)"; + << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)"; llvm_unreachable("incomplete machine model"); } #endif