[SPIRV] Support for SPV_INTEL_fpga_reg extension #134352
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EbinJose2002 commented Apr 4, 2025
EbinJose2002 commented - Support for SPV_INTEL_fpga_reg extension
- New instruction OpFPGARegINTEL added
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| @llvm/pr-subscribers-backend-spir-v @llvm/pr-subscribers-llvm-ir Author: Ebin-McW (EbinJose2002) Changes
Patch is 24.38 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/134352.diff 8 Files Affected:
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td index 4389b86745d7f..f18549f9f1191 100644 --- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td +++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td @@ -40,6 +40,7 @@ let TargetPrefix = "spv" in { def int_spv_alloca_array : Intrinsic<[llvm_any_ty], [llvm_anyint_ty, llvm_i8_ty], [ImmArg<ArgIndex<1>>]>; def int_spv_undef : Intrinsic<[llvm_i32_ty], []>; def int_spv_inline_asm : Intrinsic<[], [llvm_metadata_ty, llvm_metadata_ty, llvm_vararg_ty]>; + def int_spv_fpga : DefaultAttrsIntrinsic<[llvm_any_ty],[LLVMMatchType<0>]>; // Expect, Assume Intrinsics def int_spv_assume : Intrinsic<[], [llvm_i1_ty]>; diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp index 37119bf01545c..046e8ce03e3ff 100644 --- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp @@ -92,7 +92,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>> {"SPV_INTEL_long_composites", SPIRV::Extension::Extension::SPV_INTEL_long_composites}, {"SPV_INTEL_fp_max_error", - SPIRV::Extension::Extension::SPV_INTEL_fp_max_error}}; + SPIRV::Extension::Extension::SPV_INTEL_fp_max_error}, + {"SPV_INTEL_fpga_reg", + SPIRV::Extension::Extension::SPV_INTEL_fpga_reg}}; bool SPIRVExtensionsParser::parse(cl::Option &O, llvm::StringRef ArgName, llvm::StringRef ArgValue, diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td index 14f4f53c4cca3..c9f2434c712a4 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td +++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td @@ -928,3 +928,7 @@ def OpAliasScopeDeclINTEL: Op<5912, (outs ID:$res), (ins ID:$AliasDomain, variab "$res = OpAliasScopeDeclINTEL $AliasDomain">; def OpAliasScopeListDeclINTEL: Op<5913, (outs ID:$res), (ins variable_ops), "$res = OpAliasScopeListDeclINTEL">; + +//SPV_INTEL_fpga_reg +def OpFPGARegINTEL: Op<5949, (outs ID:$Result), (ins TYPE:$ResultType, ID:$Input), + "$Result = OpFPGARegINTEL $ResultType $Input">; diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index 4f94d9c5ebb11..f6bbdf003e6ca 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -187,6 +187,8 @@ class SPIRVInstructionSelector : public InstructionSelector { MachineInstr &I) const; bool selectDiscard(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const; + bool selectFpga(Register ResVReg, const SPIRVType *ResType, + MachineInstr &I) const; bool selectICmp(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const; @@ -2410,6 +2412,16 @@ bool SPIRVInstructionSelector::selectSplatVector(Register ResVReg, return MIB.constrainAllUses(TII, TRI, RBI); } +bool SPIRVInstructionSelector::selectFpga(Register ResVReg, + const SPIRVType *ResType, + MachineInstr &I) const { + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFPGARegINTEL)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(I.getOperand(2).getReg()); + return true; +} + bool SPIRVInstructionSelector::selectDiscard(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { @@ -3177,6 +3189,9 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, case Intrinsic::spv_discard: { return selectDiscard(ResVReg, ResType, I); } + case Intrinsic::spv_fpga: { + return selectFpga(ResVReg, ResType, I); + } default: { std::string DiagMsg; raw_string_ostream OS(DiagMsg); diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp index acc8c014cb26b..7a34474412e41 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp @@ -1772,6 +1772,15 @@ void addInstrRequirements(const MachineInstr &MI, Reqs.addCapability(SPIRV::Capability::LongCompositesINTEL); break; } + case SPIRV::OpFPGARegINTEL: { + if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_fpga_reg)) + report_fatal_error("Continued instructions require the " + "following SPIR-V extension: SPV_INTEL_fpga_reg", + false); + Reqs.addExtension(SPIRV::Extension::SPV_INTEL_fpga_reg); + Reqs.addCapability(SPIRV::Capability::FPGARegINTEL); + break; + } default: break; diff --git a/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp b/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp index 028699e56a946..35c1c952e048f 100644 --- a/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp @@ -243,6 +243,22 @@ static SmallVector<Metadata *> parseAnnotation(Value *I, : SmallVector<Metadata *>{}; } +static bool lowerAnnotation(IntrinsicInst *II) { + std::string Anno = + getAnnotation(II->getArgOperand(1), + 4 < II->arg_size() ? II->getArgOperand(4) : nullptr); + if (Anno == "__builtin_intel_fpga_reg") { + Value *val = II->getOperand(0); + IRBuilder<> IRB(II->getParent()); + IRB.SetInsertPoint(II); + Value *intrinsicVal = IRB.CreateIntrinsic(II->getOperand(0)->getType(), + Intrinsic::spv_fpga, {val}); + II->replaceAllUsesWith(intrinsicVal); + return true; + } + return false; +} + static void lowerPtrAnnotation(IntrinsicInst *II) { LLVMContext &Ctx = II->getContext(); Type *Int32Ty = Type::getInt32Ty(Ctx); @@ -256,6 +272,7 @@ static void lowerPtrAnnotation(IntrinsicInst *II) { std::string Anno = getAnnotation(II->getArgOperand(1), 4 < II->arg_size() ? II->getArgOperand(4) : nullptr); + Value *ReplacementValue = PtrArg; // Parse the annotation. SmallVector<Metadata *> MDs = parseAnnotation(II, Anno, Ctx, Int32Ty); @@ -264,6 +281,14 @@ static void lowerPtrAnnotation(IntrinsicInst *II) { // format used and output it as a general UserSemantic decoration. // Otherwise MDs is a Metadata tuple (a decoration list) in the format // expected by `spirv.Decorations`. + + if (Anno == "__builtin_intel_fpga_reg") { + Value *val = II->getOperand(0); + IRBuilder<> IRB(II->getParent()); + IRB.SetInsertPoint(II); + ReplacementValue = + IRB.CreateIntrinsic(PtrArg->getType(), Intrinsic::spv_fpga, {val}); + } if (MDs.size() == 0) { auto UserSemantic = ConstantAsMetadata::get(ConstantInt::get( Int32Ty, static_cast<uint32_t>(SPIRV::Decoration::UserSemantic))); @@ -276,7 +301,7 @@ static void lowerPtrAnnotation(IntrinsicInst *II) { IRB.CreateIntrinsic( Intrinsic::spv_assign_decoration, {PtrArg->getType()}, {PtrArg, MetadataAsValue::get(Ctx, MDNode::get(Ctx, MDs))}); - II->replaceAllUsesWith(II->getOperand(0)); + II->replaceAllUsesWith(ReplacementValue); } static void lowerFunnelShifts(IntrinsicInst *FSHIntrinsic) { @@ -423,6 +448,14 @@ bool SPIRVPrepareFunctions::substituteIntrinsicCalls(Function *F) { lowerPtrAnnotation(II); Changed = true; break; + case Intrinsic::annotation: { + const SPIRVSubtarget &STI = TM.getSubtarget<SPIRVSubtarget>(*F); + if (STI.canUseExtension(SPIRV::Extension::SPV_INTEL_fpga_reg)) { + if (lowerAnnotation(II)) + Changed = true; + } + break; + } } } } diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td index caee778eddbc4..c4c99fb3648d3 100644 --- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td +++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td @@ -513,6 +513,7 @@ defm LongCompositesINTEL : CapabilityOperand<6089, 0, 0, [SPV_INTEL_long_composi defm BindlessImagesINTEL : CapabilityOperand<6528, 0, 0, [SPV_INTEL_bindless_images], []>; defm MemoryAccessAliasingINTEL : CapabilityOperand<5910, 0, 0, [SPV_INTEL_memory_access_aliasing], []>; defm FPMaxErrorINTEL : CapabilityOperand<6169, 0, 0, [SPV_INTEL_fp_max_error], []>; +defm FPGARegINTEL : CapabilityOperand<5948, 0, 0, [SPV_INTEL_fpga_reg], []>; //===----------------------------------------------------------------------===// // Multiclass used to define SourceLanguage enum values and at the same time diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fpga_reg/IntelFPGAReg.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fpga_reg/IntelFPGAReg.ll new file mode 100644 index 0000000000000..5ac5cf8cdd513 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fpga_reg/IntelFPGAReg.ll @@ -0,0 +1,329 @@ +; LLVM IR for the test can be generated by SYCL Clang Compiler - +; see https://github.com/intel/llvm +; SYCL source code can be found below: + +; struct st { +; int a; +; float b; +; }; +; +; union un { +; int a; +; char c[4]; +; }; +; +; class A { +; public: +; A(int a) { +; m_val = a; +; } +; A(const A &a) { +; m_val = a.m_val; +; } +; private: +; int m_val; +; }; +; +; typedef int myInt; + +; void foo() { +; int a=123; +; myInt myA = 321; +; int b = __builtin_intel_fpga_reg(a); +; int myB = __builtin_intel_fpga_reg(myA); +; int c = __builtin_intel_fpga_reg(2.0f); +; int d = __builtin_intel_fpga_reg( __builtin_intel_fpga_reg( b+12 )); +; int e = __builtin_intel_fpga_reg( __builtin_intel_fpga_reg( a+b )); +; int f; +; f = __builtin_intel_fpga_reg(a); +; +; struct st i = {1, 5.0f}; +; struct st i2 = i; +; struct st ii = __builtin_intel_fpga_reg(i); +; struct st iii; +; iii = __builtin_intel_fpga_reg(ii); +; +; struct st *iiii = __builtin_intel_fpga_reg(&iii); +; +; union un u1 = {1}; +; union un u2, *u3; +; u2 = __builtin_intel_fpga_reg(u1); +; +; u3 = __builtin_intel_fpga_reg(&u2); +; +; A ca(213); +; A cb = __builtin_intel_fpga_reg(ca); +; } + +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_fpga_reg %s -o - | FileCheck %s + + +; CHECK: OpCapability FPGARegINTEL +; CHECK: OpExtension "SPV_INTEL_fpga_reg" + +; CHECK-DAG: %[[#TYPE_INT64:]] = OpTypeInt 64 0 +; CHECK-DAG: %[[#TYPE_INT32:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#TYPE_INT8:]] = OpTypeInt 8 0 +; CHECK-DAG: %[[#TYPE_PTR:]] = OpTypePointer Function %[[#TYPE_INT8]] + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" +target triple = "spir64-unknown-linux" + +%struct._ZTS2st.st = type { i32, float } +%union._ZTS2un.un = type { i32 } +%"class._ZTSZ4mainE3$_0.anon" = type { i8 } +%class._ZTS1A.A = type { i32 } + +$_ZN1AC1Ei = comdat any + +$_ZN1AC2Ei = comdat any + +@.str = private unnamed_addr addrspace(1) constant [25 x i8] c"__builtin_intel_fpga_reg\00", section "llvm.metadata" +@.str.1 = private unnamed_addr addrspace(1) constant [9 x i8] c"test.cpp\00", section "llvm.metadata" +@__const._Z3foov.i = private unnamed_addr addrspace(1) constant %struct._ZTS2st.st { i32 1, float 5.000000e+00 }, align 4 +@__const._Z3foov.u1 = private unnamed_addr addrspace(1) constant %union._ZTS2un.un { i32 1 }, align 4 + +; Function Attrs: nounwind +define spir_kernel void @_ZTSZ4mainE11fake_kernel() #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !4 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !4 { +entry: + %0 = alloca %"class._ZTSZ4mainE3$_0.anon", align 1 + call void @llvm.lifetime.start.p0(i64 1, ptr %0) #4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + call spir_func void @"_ZZ4mainENK3$_0clEv"(ptr addrspace(4) %1) + call void @llvm.lifetime.end.p0(i64 1, ptr %0) #4 + ret void +} + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 + +; Function Attrs: inlinehint nounwind +define internal spir_func void @"_ZZ4mainENK3$_0clEv"(ptr addrspace(4) %this) #2 align 2 { +entry: + %this.addr = alloca ptr addrspace(4), align 8 + store ptr addrspace(4) %this, ptr %this.addr, align 8 + %this1 = load ptr addrspace(4), ptr %this.addr, align 8 + call spir_func void @_Z3foov() + ret void +} + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 + +; Function Attrs: nounwind +define spir_func void @_Z3foov() #3 { +entry: + %a = alloca i32, align 4 + %myA = alloca i32, align 4 + %b = alloca i32, align 4 + %myB = alloca i32, align 4 + %c = alloca i32, align 4 + %d = alloca i32, align 4 + %e = alloca i32, align 4 + %f = alloca i32, align 4 + %i = alloca %struct._ZTS2st.st, align 4 + %i2 = alloca %struct._ZTS2st.st, align 4 + %ii = alloca %struct._ZTS2st.st, align 4 + %agg-temp = alloca %struct._ZTS2st.st, align 4 + %iii = alloca %struct._ZTS2st.st, align 4 + %ref.tmp = alloca %struct._ZTS2st.st, align 4 + %agg-temp2 = alloca %struct._ZTS2st.st, align 4 + %iiii = alloca ptr addrspace(4), align 8 + %u1 = alloca %union._ZTS2un.un, align 4 + %u2 = alloca %union._ZTS2un.un, align 4 + %u3 = alloca ptr addrspace(4), align 8 + %ref.tmp3 = alloca %union._ZTS2un.un, align 4 + %agg-temp4 = alloca %union._ZTS2un.un, align 4 + %ca = alloca %class._ZTS1A.A, align 4 + %cb = alloca %class._ZTS1A.A, align 4 + %agg-temp5 = alloca %class._ZTS1A.A, align 4 + %ap = alloca ptr addrspace(4), align 8 + %bp = alloca ptr addrspace(4), align 8 + call void @llvm.lifetime.start.p0(i64 4, ptr %a) #4 + store i32 123, ptr %a, align 4 + call void @llvm.lifetime.start.p0(i64 4, ptr %myA) #4 + store i32 321, ptr %myA, align 4 + call void @llvm.lifetime.start.p0(i64 4, ptr %b) #4 + %0 = load i32, ptr %a, align 4 + ; CHECK: %[[#]] = OpFPGARegINTEL %[[#TYPE_INT32]] %[[#]] + %1 = call i32 @llvm.annotation.i32.p1(i32 %0, ptr addrspace(1) @.str, ptr addrspace(1) @.str.1, i32 35) + store i32 %1, ptr %b, align 4 + call void @llvm.lifetime.start.p0(i64 4, ptr %myB) #4 + %2 = load i32, ptr %myA, align 4 + ; CHECK: %[[#]] = OpFPGARegINTEL %[[#TYPE_INT32]] %[[#]] + %3 = call i32 @llvm.annotation.i32.p1(i32 %2, ptr addrspace(1) @.str, ptr addrspace(1) @.str.1, i32 39) + store i32 %3, ptr %myB, align 4 + call void @llvm.lifetime.start.p0(i64 4, ptr %c) #4 + ; CHECK: %[[#]] = OpFPGARegINTEL %[[#TYPE_INT32]] %[[#]] + %4 = call i32 @llvm.annotation.i32.p1(i32 1073741824, ptr addrspace(1) @.str, ptr addrspace(1) @.str.1, i32 43) + %5 = bitcast i32 %4 to float + %conv = fptosi float %5 to i32 + store i32 %conv, ptr %c, align 4 + call void @llvm.lifetime.start.p0(i64 4, ptr %d) #4 + %6 = load i32, ptr %b, align 4 + %add = add nsw i32 %6, 12 + ; CHECK: %[[#]] = OpFPGARegINTEL %[[#TYPE_INT32]] %[[#]] + + %7 = call i32 @llvm.annotation.i32.p1(i32 %add, ptr addrspace(1) @.str, ptr addrspace(1) @.str.1, i32 48) + ; CHECK: %[[#]] = OpFPGARegINTEL %[[#TYPE_INT32]] %[[#]] + %8 = call i32 @llvm.annotation.i32.p1(i32 %7, ptr addrspace(1) @.str, ptr addrspace(1) @.str.1, i32 48) + store i32 %8, ptr %d, align 4 + call void @llvm.lifetime.start.p0(i64 4, ptr %e) #4 + %9 = load i32, ptr %a, align 4 + %10 = load i32, ptr %b, align 4 + %add1 = add nsw i32 %9, %10 + ; CHECK: %[[#]] = OpFPGARegINTEL %[[#TYPE_INT32]] %[[#]] + %11 = call i32 @llvm.annotation.i32.p1(i32 %add1, ptr addrspace(1) @.str, ptr addrspace(1) @.str.1, i32 54) + ; CHECK: %[[#]] = OpFPGARegINTEL %[[#TYPE_INT32]] %[[#]] + %12 = call i32 @llvm.annotation.i32.p1(i32 %11, ptr addrspace(1) @.str, ptr addrspace(1) @.str.1, i32 54) + store i32 %12, ptr %e, align 4 + call void @llvm.lifetime.start.p0(i64 4, ptr %f) #4 + %13 = load i32, ptr %a, align 4 + ; CHECK: %[[#]] = OpFPGARegINTEL %[[#TYPE_INT32]] %[[#]] + %14 = call i32 @llvm.annotation.i32.p1(i32 %13, ptr addrspace(1) @.str, ptr addrspace(1) @.str.1, i32 62) + store i32 %14, ptr %f, align 4 + call void @llvm.lifetime.start.p0(i64 8, ptr %i) #4 + call void @llvm.memcpy.p0.p1.i64(ptr align 4 %i, ptr addrspace(1) align 4 @__const._Z3foov.i, i64 8, i1 false) + call void @llvm.lifetime.start.p0(i64 8, ptr %i2) #4 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %i2, ptr align 4 %i, i64 8, i1 false) + call void @llvm.lifetime.start.p0(i64 8, ptr %ii) #4 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg-temp, ptr align 4 %i, i64 8, i1 false) + ; CHECK: %[[#]] = OpFPGARegINTEL %[[#TYPE_PTR]] %[[#]] + %15 = call ptr @llvm.ptr.annotation.p0.p1(ptr %agg-temp, ptr addrspace(1) @.str, ptr addrspace(1) @.str.1, i32 69, ptr addrspace(1) null) + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %ii, ptr align 4 %15, i64 8, i1 false) + call void @llvm.lifetime.start.p0(i64 8, ptr %iii) #4 + call void @llvm.lifetime.start.p0(i64 8, ptr %ref.tmp) #4 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg-temp2, ptr align 4 %ii, i64 8, i1 false) + ; CHECK: %[[#]] = OpFPGARegINTEL %[[#TYPE_PTR]] %[[#]] + %16 = call ptr @llvm.ptr.annotation.p0.p1(ptr %agg-temp2, ptr addrspace(1) @.str, ptr addrspace(1) @.str.1, i32 80, ptr addrspace(1) null) + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %ref.tmp, ptr align 4 %16, i64 8, i1 false) + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %iii, ptr align 4 %ref.tmp, i64 8, i1 false) + call void @llvm.lifetime.end.p0(i64 8, ptr %ref.tmp) #4 + call void @llvm.lifetime.start.p0(i64 8, ptr %iiii) #4 + %17 = ptrtoint ptr %iii to i64 + ; CHECK: %[[#]] = OpFPGARegINTEL %[[#TYPE_INT64]] %[[#]] + %18 = call i64 @llvm.annotation.i64(i64 %17, ptr addrspace(1) @.str, ptr addrspace(1) @.str.1, i32 94) + %19 = inttoptr i64 %18 to ptr + %20 = addrspacecast ptr %19 to ptr addrspace(4) + store ptr addrspace(4) %20, ptr %iiii, align 8 + call void @llvm.lifetime.start.p0(i64 4, ptr %u1) #4 + call void @llvm.memcpy.p0.p1.i64(ptr align 4 %u1, ptr addrspace(1) align 4 @__const._Z3foov.u1, i64 4, i1 false) + call void @llvm.lifetime.start.p0(i64 4, ptr %u2) #4 + call void @llvm.lifetime.start.p0(i64 8, ptr %u3) #4 + call void @llvm.lifetime.start.p0(i64 4, ptr %ref.tmp3) #4 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg-temp4, ptr align 4 %u1, i64 4, i1 false) + ; CHECK: %[[#]] = OpFPGARegINTEL %[[#TYPE_PTR]] %[[#]] + %21 = call ptr @llvm.ptr.annotation.p0.p1(ptr %agg-temp4, ptr addrspace(1) @.str, ptr addrspace(1) @.str.1, i32 103, ptr addrspace(1) null) + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %ref.tmp3, ptr align 4 %21, i64 8, i1 false) + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %u2, ptr align 4 %ref.tmp3, i64 4, i1 false) + call void @llvm.lifetime.end.p0(i64 4, ptr %ref.tmp3) #4 + %22 = ptrtoint ptr %u2 to i64 + ; CHECK: %[[#]] = OpFPGARegINTEL %[[#TYPE_INT64]] %[[#]] + %23 = call i64 @llvm.annotation.i64(i64 %22, ptr addrspace(1) @.str, ptr addrspace(1) @.str.1, i32 117) + %24 = inttoptr i64 %23 to ptr + %25 = addrspacecast ptr %24 to ptr addrspace(4) + store ptr addrspace(4) %25, ptr %u3, align 8 + call void @llvm.lifetime.start.p0(i64 4, ptr %ca) #4 + %26 = addrspacecast ptr %ca to ptr addrspace(4) + call spir_func void @_ZN1AC1Ei(ptr addrspace(4) %26, i32 213) + call void @llvm.lifetime.start.p0(i64 4, ptr %cb) #4 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg-temp5, ptr align 4 %ca, i64 4, i1 false) + ; CHECK: %[[#]] = OpFPGARegINTEL %[[#TYPE_PTR]] %[[#]] + %27 = call ptr @llvm.ptr.annotation.p0.p1(ptr %agg-temp5, ptr addrspace(1) @.str, ptr addrspace(1) @.str.1, i32 125, ptr addrspace(1) null) + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %cb, ptr align 4 %27, i64 8, i1 false) + call void @llvm.lifetime.start.p0(i64 8, ptr %ap) #4 + %28 = addrspacecast ptr %a to ptr addrspace(4) + store ptr addrspace(4) %28, ptr %ap, align 8 + call void @llvm.lifetime.start.p0(i64 8, ptr %bp) #4 + %29 = load ptr addrspace(4), ptr %ap, align 8 + %30 = ptrtoint ptr addrspace(4) %29 to i64 + ; CHECK: %[[#]] = OpFPGARegINTEL %[[#TYPE_INT64]] %[[#]] + %31 = call i64 @llvm.annotation.i64(i64 %30, ptr addrspace(1) @.str, ptr addrspace(1) @.str.1, i32 137) + %32 = inttoptr i64 %31 to ptr addrspace(4) + store ptr addrspace(4) %32, ptr %bp, align 8 + call void @llvm.lifetime.end.p0(i64 8, ptr %bp) #4 + call void @llvm.lifetim... [truncated] |
- New instruction OpFPGARegINTEL added
MrSidims reviewed May 6, 2025
| } | ||
| case SPIRV::OpFPGARegINTEL: { | ||
| if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_fpga_reg)) | ||
| report_fatal_error("Continued instructions require the " |
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Suggested change
| report_fatal_error("Continued instructions require the " | |
| report_fatal_error("OpFPGARegINTEL instruction requires the " |
| std::string Anno = | ||
| getAnnotation(II->getArgOperand(1), | ||
| 4 < II->arg_size() ? II->getArgOperand(4) : nullptr); | ||
| if (Anno == "__builtin_intel_fpga_reg") { |
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This is an internal builtin used in https://github.com/intel/llvm , so if you really want to use it in SPIR-V backend, then probably it should be upstreamed to LLVM itself. Depending on your goals it is also worth considering to step away from intel/llvm and llvm-spirv implementation and instead represent fpga_reg as an intrinsic function, leaving the compiler's frontend to emit it.
If you could help with understanding your upstreaming efforts - may be a can give some suggestions.
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I’ll try going ahead with a generic LLVM intrinsic for fpga_reg and have Clang emit it directly. That should keep things cleaner and not tied to the intel/llvm.
If you have any suggestions on the intrinsic definition please let me know.
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One question though, I haven't seen any similar intel builtins being handled in clang. So is mapping this builtin to a new intrinsic in clang is the best approach ?
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@AaronBallman could you please advise us here?
My understanding that it should be either upstreaming handling of the builtin from https://github.com/intel/llvm/blob/sycl/clang/lib/CodeGen/CGBuiltin.cpp#L6377 to llvm.org (so this __builtin_intel_fpga_reg string wouldn't be 'magical' for llvm.org) or adding a brand-new intrinsic for this.
Pros for the upstream:
- everything would work out of the box for SPIR-V backend and LLVM IR to SPIR-V translator;
Cons:
- I'm not sure how clang folks would react on this, that is why I called Aaron for help;
- As you see, intel/llvm implementation uses
annotationintrinsics for this, and LangRef says about them:
"These have no other defined use; transformations preserve annotations on a best-effort basis but are allowed to replace the intrinsic with its first argument without breaking semantics and the intrinsic is completely dropped during instruction selection."
For SYCL compiler in intel/llvm it is (was) fine, as for FPGA the code is (was) always compiled with disabled frontend optimizations and the appropriate annotation intrinsics always survive until SPIR-V is generated. I don't know what design do you have an how you will use the extension E2E to claim, that annotations will also work fine for your flow.
I'm saying is(was) because FPGA support is being removed from intel/llvm due to Altera spin-off. So lets call @aejjehint here to check, what Altera folks think about this (I'm not sure if you @EbinJose2002 come from Altera or from other company :) )
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@AaronBallman could you please advise us here?
My understanding that it should be either upstreaming handling of the builtin from https://github.com/intel/llvm/blob/sycl/clang/lib/CodeGen/CGBuiltin.cpp#L6377 to llvm.org (so this
__builtin_intel_fpga_regstring wouldn't be 'magical' for llvm.org) or adding a brand-new intrinsic for this.Pros for the upstream:
* everything would work out of the box for SPIR-V backend and LLVM IR to SPIR-V translator;Cons:
* I'm not sure how clang folks would react on this, that is why I called Aaron for help;
I think introducing a new builtin to upstream Clang would be reasonable for this, but
* As you see, intel/llvm implementation uses `annotation` intrinsics for this, and LangRef says about them: "These have no other defined use; **transformations preserve annotations on a best-effort basis but are allowed to replace the intrinsic with its first argument** without breaking semantics and the intrinsic is completely dropped during instruction selection." For SYCL compiler in intel/llvm it is (was) fine, as for FPGA the code is (was) always compiled with disabled frontend optimizations and the appropriate annotation intrinsics always survive until SPIR-V is generated. I don't know what design do you have an how you will use the extension E2E to claim, that annotations will also work fine for your flow.
I agree that this will be a issue, I don't think an annotation is the right way to go (probably requires an LLVM intrinsic for Clang to lower the builtin to).
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I was exploring the extensions implemented in the LLVM-SPIRV translator that haven't yet been integrated into the main LLVM project. That's how I identified this particular extension.
So how should I proceed ? Can I proceed with creating an llvm intrinsic ?
Comment on lines +1 to +56
| ; LLVM IR for the test can be generated by SYCL Clang Compiler - | ||
| ; see https://github.com/intel/llvm | ||
| ; SYCL source code can be found below: | ||
| | ||
| ; struct st { | ||
| ; int a; | ||
| ; float b; | ||
| ; }; | ||
| ; | ||
| ; union un { | ||
| ; int a; | ||
| ; char c[4]; | ||
| ; }; | ||
| ; | ||
| ; class A { | ||
| ; public: | ||
| ; A(int a) { | ||
| ; m_val = a; | ||
| ; } | ||
| ; A(const A &a) { | ||
| ; m_val = a.m_val; | ||
| ; } | ||
| ; private: | ||
| ; int m_val; | ||
| ; }; | ||
| ; | ||
| ; typedef int myInt; | ||
| | ||
| ; void foo() { | ||
| ; int a=123; | ||
| ; myInt myA = 321; | ||
| ; int b = __builtin_intel_fpga_reg(a); | ||
| ; int myB = __builtin_intel_fpga_reg(myA); | ||
| ; int c = __builtin_intel_fpga_reg(2.0f); | ||
| ; int d = __builtin_intel_fpga_reg( __builtin_intel_fpga_reg( b+12 )); | ||
| ; int e = __builtin_intel_fpga_reg( __builtin_intel_fpga_reg( a+b )); | ||
| ; int f; | ||
| ; f = __builtin_intel_fpga_reg(a); | ||
| ; | ||
| ; struct st i = {1, 5.0f}; | ||
| ; struct st i2 = i; | ||
| ; struct st ii = __builtin_intel_fpga_reg(i); | ||
| ; struct st iii; | ||
| ; iii = __builtin_intel_fpga_reg(ii); | ||
| ; | ||
| ; struct st *iiii = __builtin_intel_fpga_reg(&iii); | ||
| ; | ||
| ; union un u1 = {1}; | ||
| ; union un u2, *u3; | ||
| ; u2 = __builtin_intel_fpga_reg(u1); | ||
| ; | ||
| ; u3 = __builtin_intel_fpga_reg(&u2); | ||
| ; | ||
| ; A ca(213); | ||
| ; A cb = __builtin_intel_fpga_reg(ca); | ||
| ; } |
Comment on lines +311 to +329
| attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" } | ||
| attributes #1 = { argmemonly nounwind } | ||
| attributes #2 = { inlinehint nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } | ||
| attributes #3 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } | ||
| attributes #4 = { nounwind } | ||
| | ||
| !llvm.module.flags = !{!0} | ||
| !opencl.spir.version = !{!1} | ||
| !spirv.Source = !{!2} | ||
| !llvm.ident = !{!3} | ||
| | ||
| !0 = !{i32 1, !"wchar_size", i32 4} | ||
| !1 = !{i32 1, i32 2} | ||
| !2 = !{i32 4, i32 100000} | ||
| !3 = !{!"clang version 9.0.0"} | ||
| !4 = !{} | ||
| !5 = !{!"any pointer", !6, i64 0} | ||
| !6 = !{!"omnipotent char", !7, i64 0} | ||
| !7 = !{!"Simple C++ TBAA"} |
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AFAIU attributes and metadata are also not needed.
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