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Merged
merged 3 commits into from
May 15, 2025
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[RISCV][MC] Add support for Q extension #139369

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eb15367
[RISCV][MC] Add support for Q extension
el-ev May 12, 2025
41892d8
release note
el-ev May 12, 2025
86d53f7
Merge branch 'main' into users/el-ev/riscv-q-ext
el-ev May 15, 2025
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1 change: 1 addition & 0 deletions clang/test/Driver/print-supported-extensions-riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
// CHECK-NEXT: q 2.2 'Q' (Quad-Precision Floating-Point)
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
// CHECK-NEXT: v 1.0 'V' (Vector Extension for Application Processors)
Expand Down
26 changes: 16 additions & 10 deletions clang/test/Driver/riscv-arch.c
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Expand Up @@ -10,6 +10,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv32-unknown-elf -march=rv32imafd -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv32-unknown-elf -march=rv32imafdq -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s

// RUN: %clang --target=riscv32-unknown-elf -march=rv32ic -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
Expand All @@ -21,20 +23,26 @@
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv32-unknown-elf -march=rv32imafdc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv32-unknown-elf -march=rv32imafdqc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s

// RUN: %clang --target=riscv32-unknown-elf -march=rv32ia -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv32-unknown-elf -march=rv32iaf -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv32-unknown-elf -march=rv32iafd -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv32-unknown-elf -march=rv32iafdq -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s

// RUN: %clang --target=riscv32-unknown-elf -march=rv32iac -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv32-unknown-elf -march=rv32iafc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv32-unknown-elf -march=rv32iafdc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv32-unknown-elf -march=rv32iafdqc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s

// RUN: %clang --target=riscv32-unknown-elf -march=rv32g -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
Expand Down Expand Up @@ -80,6 +88,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv64-unknown-elf -march=rv64imafd -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv64-unknown-elf -march=rv64imafdq -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s

// RUN: %clang --target=riscv64-unknown-elf -march=rv64ic -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
Expand All @@ -91,20 +101,26 @@
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv64-unknown-elf -march=rv64imafdc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv64-unknown-elf -march=rv64imafdqc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s

// RUN: %clang --target=riscv64-unknown-elf -march=rv64ia -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv64-unknown-elf -march=rv64iaf -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv64-unknown-elf -march=rv64iafd -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv64-unknown-elf -march=rv64iafdq -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s

// RUN: %clang --target=riscv64-unknown-elf -march=rv64iac -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv64-unknown-elf -march=rv64iafc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv64-unknown-elf -march=rv64iafdc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv64-unknown-elf -march=rv64iafdqc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s

// RUN: %clang --target=riscv64-unknown-elf -march=rv64g -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
Expand Down Expand Up @@ -211,11 +227,6 @@
// RV32-LETTER: error: invalid arch name 'rv32q',
// RV32-LETTER: first letter after 'rv32' should be 'e', 'i' or 'g'

// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imcq -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ORDER %s
// RV32-ORDER: error: invalid arch name 'rv32imcq',
// RV32-ORDER: unsupported standard user-level extension 'q'

// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izvl64b -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
// RV32-ZVL64B-ER: error: invalid arch name 'rv32izvl64b',
Expand All @@ -226,11 +237,6 @@
// RV32-STD-INVAL: error: invalid arch name 'rv32imw',
// RV32-STD-INVAL: invalid standard user-level extension 'w'

// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imqc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-STD %s
// RV32-STD: error: invalid arch name 'rv32imqc',
// RV32-STD: unsupported standard user-level extension 'q'

// RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
// RV32X: error: invalid arch name 'rv32xabc',
Expand Down
12 changes: 12 additions & 0 deletions clang/test/Preprocessor/riscv-target-features.c
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Expand Up @@ -20,6 +20,7 @@
// CHECK-NOT: __riscv_m {{.*$}}
// CHECK-NOT: __riscv_mul {{.*$}}
// CHECK-NOT: __riscv_muldiv {{.*$}}
// CHECK-NOT: __riscv_q {{.*$}}
// CHECK-NOT: __riscv_sha {{.*$}}
// CHECK-NOT: __riscv_shcounterenw {{.*$}}
// CHECK-NOT: __riscv_shgatpa {{.*$}}
Expand Down Expand Up @@ -334,6 +335,17 @@
// CHECK-M-EXT: __riscv_mul 1
// CHECK-M-EXT: __riscv_muldiv 1

// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32ifdq -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-Q-EXT %s
// RUN: %clang --target=riscv64-unknown-linux-gnu \
// RUN: -march=rv64ifdq -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-Q-EXT %s
// CHECK-Q-EXT: __riscv_fdiv 1
// CHECK-Q-EXT: __riscv_flen 128
// CHECK-Q-EXT: __riscv_fsqrt 1
// CHECK-Q-EXT: __riscv_q 2002000{{$}}

// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32isha -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SHCOUNTERENW-EXT %s
Expand Down
1 change: 1 addition & 0 deletions llvm/docs/RISCVUsage.rst
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Expand Up @@ -119,6 +119,7 @@ on support follow.
``E`` Supported (`See note <#riscv-rve-note>`__)
``H`` Assembly Support
``M`` Supported
``Q`` Assembly Support
``Sha`` Supported
``Shcounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Shgatpa`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
Expand Down
4 changes: 3 additions & 1 deletion llvm/docs/ReleaseNotes.md
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Expand Up @@ -187,7 +187,9 @@ Changes to the RISC-V Backend
* `-mcpu=sifive-p870` was added.
* Adds assembler support for the Andes `XAndesvpackfph` (Andes Vector Packed FP16 extension).
* Adds assembler support for the Andes `XAndesvdot` (Andes Vector Dot Product extension).

* Adds assembler support for the standard `Q` (Quad-Precision Floating Point)
extension.

Changes to the WebAssembly Backend
----------------------------------

Expand Down
22 changes: 20 additions & 2 deletions llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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Expand Up @@ -1272,6 +1272,11 @@ static MCRegister convertFPR64ToFPR32(MCRegister Reg) {
return Reg - RISCV::F0_D + RISCV::F0_F;
}

static MCRegister convertFPR64ToFPR128(MCRegister Reg) {
assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register");
return Reg - RISCV::F0_D + RISCV::F0_Q;
}

static MCRegister convertVRToVRMx(const MCRegisterInfo &RI, MCRegister Reg,
unsigned Kind) {
unsigned RegClassID;
Expand Down Expand Up @@ -1300,6 +1305,10 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg);
bool IsRegVR = RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg);

if (IsRegFPR64 && Kind == MCK_FPR128) {
Op.Reg.RegNum = convertFPR64ToFPR128(Reg);
return Match_Success;
}
// As the parser couldn't differentiate an FPR32 from an FPR64, coerce the
// register from FPR64 to FPR32 or FPR64C to FPR32C if necessary.
if ((IsRegFPR64 && Kind == MCK_FPR32) ||
Expand Down Expand Up @@ -1663,13 +1672,16 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
// rejected.
MCRegister RISCVAsmParser::matchRegisterNameHelper(StringRef Name) const {
MCRegister Reg = MatchRegisterName(Name);
// The 16-/32- and 64-bit FPRs have the same asm name. Check that the initial
// match always matches the 64-bit variant, and not the 16/32-bit one.
// The 16-/32-/128- and 64-bit FPRs have the same asm name. Check
// that the initial match always matches the 64-bit variant, and
// not the 16/32/128-bit one.
assert(!(Reg >= RISCV::F0_H && Reg <= RISCV::F31_H));
assert(!(Reg >= RISCV::F0_F && Reg <= RISCV::F31_F));
assert(!(Reg >= RISCV::F0_Q && Reg <= RISCV::F31_Q));
// The default FPR register class is based on the tablegen enum ordering.
static_assert(RISCV::F0_D < RISCV::F0_H, "FPR matching must be updated");
static_assert(RISCV::F0_D < RISCV::F0_F, "FPR matching must be updated");
static_assert(RISCV::F0_D < RISCV::F0_Q, "FPR matching must be updated");
if (!Reg)
Reg = MatchRegisterAltName(Name);
if (isRVE() && Reg >= RISCV::X16 && Reg <= RISCV::X31)
Expand Down Expand Up @@ -3848,6 +3860,9 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
case RISCV::PseudoFLD:
emitLoadStoreSymbol(Inst, RISCV::FLD, IDLoc, Out, /*HasTmpReg=*/true);
return false;
case RISCV::PseudoFLQ:
emitLoadStoreSymbol(Inst, RISCV::FLQ, IDLoc, Out, /*HasTmpReg=*/true);
return false;
case RISCV::PseudoSB:
case RISCV::PseudoQC_E_SB:
emitLoadStoreSymbol(Inst, RISCV::SB, IDLoc, Out, /*HasTmpReg=*/true);
Expand Down Expand Up @@ -3875,6 +3890,9 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
case RISCV::PseudoFSD:
emitLoadStoreSymbol(Inst, RISCV::FSD, IDLoc, Out, /*HasTmpReg=*/true);
return false;
case RISCV::PseudoFSQ:
emitLoadStoreSymbol(Inst, RISCV::FSQ, IDLoc, Out, /*HasTmpReg=*/true);
return false;
case RISCV::PseudoAddTPRel:
if (checkPseudoAddTPRel(Inst, Operands))
return true;
Expand Down
11 changes: 11 additions & 0 deletions llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
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Expand Up @@ -177,6 +177,17 @@ static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo,
return MCDisassembler::Success;
}

static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
if (RegNo >= 32)
return MCDisassembler::Fail;

MCRegister Reg = RISCV::F0_Q + RegNo;
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}

static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
Expand Down
7 changes: 7 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -292,6 +292,13 @@ def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
AssemblerPredicate<(all_of FeatureStdExtD),
"'D' (Double-Precision Floating-Point)">;

def FeatureStdExtQ
: RISCVExtension<2, 2, "Quad-Precision Floating-Point", [FeatureStdExtD]>,
RISCVExtensionBitmask<0, 16>;
def HasStdExtQ : Predicate<"Subtarget->hasStdExtQ()">,
AssemblerPredicate<(all_of FeatureStdExtQ),
"'Q' (Quad-Precision Floating-Point)">;

def FeatureStdExtZfhmin
: RISCVExtension<1, 0, "Half-Precision Floating-Point Minimal",
[FeatureStdExtF]>,
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Expand Up @@ -2220,6 +2220,7 @@ include "RISCVInstrInfoZilsd.td"
// Scalar FP
include "RISCVInstrInfoF.td"
include "RISCVInstrInfoD.td"
include "RISCVInstrInfoQ.td"
include "RISCVInstrInfoZfh.td"
include "RISCVInstrInfoZfbfmin.td"
include "RISCVInstrInfoZfa.td"
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfoF.td
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Expand Up @@ -121,7 +121,7 @@ def FPR32INX : RegisterOperand<GPRF32> {
let ParserMatchClass = GPRAsFPR32;
}

// Describes a combination of predicates from F/D/Zfh/Zfhmin or
// Describes a combination of predicates from F/D/Q/Zfh/Zfhmin or
// Zfinx/Zdinx/Zhinx/Zhinxmin that are applied to scalar FP instruction.
// Contains the DAGOperand for the primary type for the predicates. The primary
// type may be unset for combinations of predicates like Zfh+D.
Expand Down
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