[RISCV] Prefer preindexed addressing mode when XTheadMemIdx exists

[wangpc-pp]

The experimental result shows that we can generate more XTheadMemIdx
instructions when using preindexed addressing mode on SPEC CPU 2017.

-lsr-preferred-addressing-mode	Num
none	47308
preindexed	54125
postindexed	50255

[llvmbot]

@llvm/pr-subscribers-llvm-transforms

@llvm/pr-subscribers-backend-risc-v

Author: Pengcheng Wang (wangpc-pp)

Changes

The experimental result shows that we can generate more XTheadMemIdx
instructions when using preindexed addressing mode.

-lsr-preferred-addressing-mode	Num
none	47308
preindexed	54125
postindexed	50255

---

Full diff: https://github.com/llvm/llvm-project/pull/147921.diff

1 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp (+3)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index 67a51c12b508e..c07472a55c731 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -2709,6 +2709,9 @@ RISCVTTIImpl::getPreferredAddressingMode(const Loop *L, if (ST->hasVendorXCVmem() && !ST->is64Bit()) return TTI::AMK_PostIndexed; + if (ST->hasVendorXTHeadMemIdx()) + return TTI::AMK_PreIndexed; + return BasicTTIImplBase::getPreferredAddressingMode(L, SE); } 

[lenary]

Is it possible to add a test?

[lenary]

LGTM

[topperc]

Is this better than NONE. We move the pointer increment from the store to the load which didn't change the size of the loop body, but now we have an extra instruction in the preheader.