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[RISCV] Use LD_RV32/SD_RV32 for spills and reloads when Zilsd is enabled #153595
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This says align 4. SD_RV32 requires 8 byte alignment.
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:( everything is always a few more steps more complex than hoped.
We have a few ideas around addressing this so SD_RV32 is usable for these spills, but none are fundamentally easy. We'll be back with a larger proposal around this.
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I think I looked into this once.
One thing I do remember is that the alignment associated with the FrameIndex object might be wrong if the stack can't be realigned.
I'm now wondering if spills of D registers on RV32E can reliably use FSD/FLD since the stack is only 4 byte aligned. The D register spill would require stack realignment, but that might not be possible.
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Yeah. The spill alignment for pairs matches the spill alignment for GPRs, rather than matching the natural alignment of pairs.
I think increasing the spill width is possible, but would cause issues on
ilp32eas you point out, as we find it hard to spill D registers already with that combo, due to stack realignment.Thankfully, the spill alignment is not an ABI detail, so we can try to make better choices, but annoyingly it's also controlled by tablegen info which we cannot override easily (this does not warrant new HWModes, which would be the only way to change it).
We're thinking about other ideas here, including about how we are handling alignment on rv32 - but we're also in the final days before our own release freeze, so capacity for our team to do a larger fix is not available immediately.