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[RISCV] Use C.ADD when OR is not compressible due to register restriction#156044

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[RISCV] Use C.ADD when OR is not compressible due to register restriction#156044
preames wants to merge 1 commit intollvm:mainfrom
preames:pr-riscv-or-disjoint-as-add-try2

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Commits on Aug 29, 2025