[AArch64] Remove post-decoding instruction mutations #156364
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This was referenced Sep 1, 2025
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| ✅ With the latest revision this PR passed the C/C++ code formatter. |
s-barannikov force-pushed the users/s.barannikov/decoder-operands-6-aarch64-rest branch from 769d57a to ed29165 Compare s-barannikov force-pushed the users/s.barannikov/decoder-operands-5-aarch64-spill-fill branch 2 times, most recently from 5cc7d7a to 261f86f Compare s-barannikov force-pushed the users/s.barannikov/decoder-operands-6-aarch64-rest branch 3 times, most recently from a112090 to c66fd0b Compare s-barannikov force-pushed the users/s.barannikov/decoder-operands-5-aarch64-spill-fill branch from 261f86f to d72f713 Compare s-barannikov force-pushed the users/s.barannikov/decoder-operands-6-aarch64-rest branch 2 times, most recently from b60b806 to ec3ee1e Compare s-barannikov force-pushed the users/s.barannikov/decoder-operands-5-aarch64-spill-fill branch from 772f655 to 7112890 Compare s-barannikov force-pushed the users/s.barannikov/decoder-operands-6-aarch64-rest branch from ec3ee1e to 098f887 Compare s-barannikov force-pushed the users/s.barannikov/decoder-operands-5-aarch64-spill-fill branch from 7112890 to ed950c3 Compare s-barannikov force-pushed the users/s.barannikov/decoder-operands-6-aarch64-rest branch from 098f887 to 46fc93b Compare s-barannikov force-pushed the users/s.barannikov/decoder-operands-5-aarch64-spill-fill branch from ed950c3 to f3b4f27 Compare s-barannikov force-pushed the users/s.barannikov/decoder-operands-6-aarch64-rest branch 2 times, most recently from ee67c36 to 9709854 Compare s-barannikov force-pushed the users/s.barannikov/decoder-operands-5-aarch64-spill-fill branch from f3b4f27 to 6830ba2 Compare s-barannikov force-pushed the users/s.barannikov/decoder-operands-6-aarch64-rest branch from 9709854 to aa97c88 Compare s-barannikov force-pushed the users/s.barannikov/decoder-operands-5-aarch64-spill-fill branch from 6830ba2 to b95e187 Compare s-barannikov force-pushed the users/s.barannikov/decoder-operands-6-aarch64-rest branch from aa97c88 to f31a7b8 Compare s-barannikov force-pushed the users/s.barannikov/decoder-operands-5-aarch64-spill-fill branch from b95e187 to 9758552 Compare Base automatically changed from users/s.barannikov/decoder-operands-5-aarch64-spill-fill to main September 5, 2025 12:43
s-barannikov force-pushed the users/s.barannikov/decoder-operands-6-aarch64-rest branch 2 times, most recently from 607d600 to 054fefc Compare s-barannikov requested review from aaronmondal, keith and rupprecht as code owners 
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| gentle ping |
davemgreen approved these changes Sep 15, 2025
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I'm not the biggest expert here, and bits<0> seems a little unusual, but as far as I can tell this LGTM. Thanks
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It kind of makes sense if you look at related instructions, e.g.: |
These instructions can now be fully decoded automatically.
s-barannikov force-pushed the users/s.barannikov/decoder-operands-6-aarch64-rest branch from 5e59a9a to cbbc47b Compare s-barannikov deleted the users/s.barannikov/decoder-operands-6-aarch64-rest branch 
rupprecht added a commit that referenced this pull request Sep 19, 2025
This was updated in #156364 but `-ignore-non-decodable-operands` was removed from the wrong tablegen arg list (arm vs aarch64)
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| LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/18/builds/21322 Here is the relevant piece of the build log for the reference |
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| LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/168/builds/16243 Here is the relevant piece of the build log for the reference |
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| LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/72/builds/15142 Here is the relevant piece of the build log for the reference |
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Add
bits<0>fields to instructions using the ZTR/MPR/MPR8 register classes.These register classes contain only one register, and it is not encoded in the instruction.
This way, the generated decoder can completely decode instructions without having to perform a post-decoding pass to insert missing operands.
Some immediate operands are also not encoded and have only one possible value "zero". Use this trick for them, too.
Finally, remove
-ignore-non-decodable-operandsoption fromllvm-tblgeninvocation to ensure that non-decodable operands do not appear in the future.