CodeGen: Remove TRI arguments from stack load/store hooks #158240
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arsenm added backend:AArch64 backend:AMDGPU backend:ARC backend:ARM backend:CSKY backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:globalisel llvm:regalloc llvm:SelectionDAG 
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arsenm requested review from MatzeB, RKSimon, phoebewang, preames, qcolombet, s-barannikov and topperc 
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| @llvm/pr-subscribers-backend-systemz @llvm/pr-subscribers-backend-msp430 Author: Matt Arsenault (arsenm) ChangesThis is directly available in TargetInstrInfo Patch is 110.41 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/158240.diff 63 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h index 802cca6022074..fb7ced7960846 100644 --- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h +++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h @@ -1165,8 +1165,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo { /// register spill instruction, part of prologue, during the frame lowering. virtual void storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, - bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const { llvm_unreachable("Target didn't implement " "TargetInstrInfo::storeRegToStackSlot!"); @@ -1184,8 +1183,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo { /// register reload instruction, part of epilogue, during the frame lowering. virtual void loadRegFromStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg, + int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const { llvm_unreachable("Target didn't implement " "TargetInstrInfo::loadRegFromStackSlot!"); diff --git a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp index 8b74dcebd00ac..c23cac7974d51 100644 --- a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp +++ b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp @@ -420,7 +420,7 @@ class StatepointState { LLVM_DEBUG(dbgs() << "Insert spill before " << *InsertBefore); TII.storeRegToStackSlot(*MI.getParent(), InsertBefore, Reg, IsKill, FI, - RC, &TRI, Register()); + RC, Register()); } } @@ -429,7 +429,7 @@ class StatepointState { const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); int FI = RegToSlotIdx[Reg]; if (It != MBB->end()) { - TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI, Register()); + TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, Register()); return; } @@ -437,7 +437,7 @@ class StatepointState { // and then swap them. assert(!MBB->empty() && "Empty block"); --It; - TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI, Register()); + TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, Register()); MachineInstr *Reload = It->getPrevNode(); int Dummy = 0; (void)Dummy; diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp index 98c56f739ad4e..80e096cb42cda 100644 --- a/llvm/lib/CodeGen/InlineSpiller.cpp +++ b/llvm/lib/CodeGen/InlineSpiller.cpp @@ -473,7 +473,7 @@ bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI, MachineInstrSpan MIS(MII, MBB); // Insert spill without kill flag immediately after def. TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot, - MRI.getRegClass(SrcReg), &TRI, Register()); + MRI.getRegClass(SrcReg), Register()); LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MII); for (const MachineInstr &MI : make_range(MIS.begin(), MII)) getVDefInterval(MI, LIS); @@ -1098,7 +1098,7 @@ void InlineSpiller::insertReload(Register NewVReg, MachineInstrSpan MIS(MI, &MBB); TII.loadRegFromStackSlot(MBB, MI, NewVReg, StackSlot, - MRI.getRegClass(NewVReg), &TRI, Register()); + MRI.getRegClass(NewVReg), Register()); LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI); @@ -1134,7 +1134,7 @@ void InlineSpiller::insertSpill(Register NewVReg, bool isKill, if (IsRealSpill) TII.storeRegToStackSlot(MBB, SpillBefore, NewVReg, isKill, StackSlot, - MRI.getRegClass(NewVReg), &TRI, Register()); + MRI.getRegClass(NewVReg), Register()); else // Don't spill undef value. // Anything works for undef, in particular keeping the memory @@ -1708,7 +1708,7 @@ void HoistSpillHelper::hoistAllSpills() { MachineBasicBlock::iterator MII = IPA.getLastInsertPointIter(OrigLI, *BB); MachineInstrSpan MIS(MII, BB); TII.storeRegToStackSlot(*BB, MII, LiveReg, false, Slot, - MRI.getRegClass(LiveReg), &TRI, Register()); + MRI.getRegClass(LiveReg), Register()); LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MII); for (const MachineInstr &MI : make_range(MIS.begin(), MII)) getVDefInterval(MI, LIS); diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp index 804480cdd8e6f..417b11b3f04bd 100644 --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -594,8 +594,7 @@ void RegAllocFastImpl::spill(MachineBasicBlock::iterator Before, LLVM_DEBUG(dbgs() << " to stack slot #" << FI << '\n'); const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); - TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI, - VirtReg); + TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, VirtReg); ++NumStores; MachineBasicBlock::iterator FirstTerm = MBB->getFirstTerminator(); @@ -652,7 +651,7 @@ void RegAllocFastImpl::reload(MachineBasicBlock::iterator Before, << printReg(PhysReg, TRI) << '\n'); int FI = getStackSpaceFor(VirtReg); const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); - TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI, VirtReg); + TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, VirtReg); ++NumLoads; } @@ -1123,7 +1122,7 @@ bool RegAllocFastImpl::defineVirtReg(MachineInstr &MI, unsigned OpNum, if (MO.isMBB()) { MachineBasicBlock *Succ = MO.getMBB(); TII->storeRegToStackSlot(*Succ, Succ->begin(), PhysReg, Kill, FI, - &RC, TRI, VirtReg); + &RC, VirtReg); ++NumStores; Succ->addLiveIn(PhysReg); } diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp index 7e26c2ed59949..d8861672a348f 100644 --- a/llvm/lib/CodeGen/RegisterScavenging.cpp +++ b/llvm/lib/CodeGen/RegisterScavenging.cpp @@ -276,14 +276,14 @@ RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj, ": Cannot scavenge register without an emergency " "spill slot!"); } - TII->storeRegToStackSlot(*MBB, Before, Reg, true, FI, &RC, TRI, Register()); + TII->storeRegToStackSlot(*MBB, Before, Reg, true, FI, &RC, Register()); MachineBasicBlock::iterator II = std::prev(Before); unsigned FIOperandNum = getFrameIndexOperandNum(*II); TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this); // Restore the scavenged register before its use (or first terminator). - TII->loadRegFromStackSlot(*MBB, UseMI, Reg, FI, &RC, TRI, Register()); + TII->loadRegFromStackSlot(*MBB, UseMI, Reg, FI, &RC, Register()); II = std::prev(UseMI); FIOperandNum = getFrameIndexOperandNum(*II); diff --git a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp index 70c3b2cbae9a6..ebf6d1a52448e 100644 --- a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp +++ b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp @@ -198,7 +198,7 @@ void TargetFrameLowering::spillCalleeSavedRegister( } else { const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); TII->storeRegToStackSlot(SaveBlock, MI, Reg, true, CS.getFrameIdx(), RC, - TRI, Register()); + Register()); } } @@ -212,8 +212,7 @@ void TargetFrameLowering::restoreCalleeSavedRegister( .addReg(CS.getDstReg(), getKillRegState(true)); } else { const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); - TII->loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI, - Register()); + TII->loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, Register()); assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!"); } } diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp index e186932d88309..037ca98f6cff8 100644 --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -792,11 +792,11 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI, // code. BuildMI(*MBB, Pos, MI.getDebugLoc(), get(TargetOpcode::KILL)).add(MO); } else { - storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, &TRI, + storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, Register()); } } else - loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, &TRI, Register()); + loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, Register()); return &*--Pos; } diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index 175b5e04d82ff..a1f271554b4fc 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -3732,7 +3732,7 @@ struct ScopedScavengeOrSpill { } FreeReg = SpillCandidate; SpillFI = MaybeSpillFI->value(); - TII.storeRegToStackSlot(MBB, MBBI, FreeReg, false, *SpillFI, &RC, &TRI, + TII.storeRegToStackSlot(MBB, MBBI, FreeReg, false, *SpillFI, &RC, Register()); } @@ -3745,8 +3745,7 @@ struct ScopedScavengeOrSpill { ~ScopedScavengeOrSpill() { if (hasSpilled()) - TII.loadRegFromStackSlot(MBB, MBBI, FreeReg, *SpillFI, &RC, &TRI, - Register()); + TII.loadRegFromStackSlot(MBB, MBBI, FreeReg, *SpillFI, &RC, Register()); } private: diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 19f421a4a081b..dc804611e27ce 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -5565,7 +5565,6 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags) const { MachineFunction &MF = *MBB.getParent(); @@ -5579,7 +5578,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, bool Offset = true; MCRegister PNRReg = MCRegister::NoRegister; unsigned StackID = TargetStackID::Default; - switch (TRI->getSpillSize(*RC)) { + switch (RI.getSpillSize(*RC)) { case 1: if (AArch64::FPR8RegClass.hasSubClassEq(RC)) Opc = AArch64::STRBui; @@ -5747,10 +5746,12 @@ static void loadRegPairFromStackSlot(const TargetRegisterInfo &TRI, .addMemOperand(MMO); } -void AArch64InstrInfo::loadRegFromStackSlot( - MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, - int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg, MachineInstr::MIFlag Flags) const { +void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + Register DestReg, int FI, + const TargetRegisterClass *RC, + Register VReg, + MachineInstr::MIFlag Flags) const { MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI); @@ -5762,7 +5763,7 @@ void AArch64InstrInfo::loadRegFromStackSlot( bool Offset = true; unsigned StackID = TargetStackID::Default; Register PNRReg = MCRegister::NoRegister; - switch (TRI->getSpillSize(*RC)) { + switch (TRI.getSpillSize(*RC)) { case 1: if (AArch64::FPR8RegClass.hasSubClassEq(RC)) Opc = AArch64::LDRBui; @@ -6394,10 +6395,10 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl( "Mismatched register size in non subreg COPY"); if (IsSpill) storeRegToStackSlot(MBB, InsertPt, SrcReg, SrcMO.isKill(), FrameIndex, - getRegClass(SrcReg), &TRI, Register()); + getRegClass(SrcReg), Register()); else loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex, - getRegClass(DstReg), &TRI, Register()); + getRegClass(DstReg), Register()); return &*--InsertPt; } @@ -6415,8 +6416,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl( assert(SrcMO.getSubReg() == 0 && "Unexpected subreg on physical register"); storeRegToStackSlot(MBB, InsertPt, AArch64::XZR, SrcMO.isKill(), - FrameIndex, &AArch64::GPR64RegClass, &TRI, - Register()); + FrameIndex, &AArch64::GPR64RegClass, Register()); return &*--InsertPt; } @@ -6450,7 +6450,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl( assert(TRI.getRegSizeInBits(*getRegClass(SrcReg)) == TRI.getRegSizeInBits(*FillRC) && "Mismatched regclass size on folded subreg COPY"); - loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex, FillRC, &TRI, + loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex, FillRC, Register()); MachineInstr &LoadMI = *--InsertPt; MachineOperand &LoadDst = LoadMI.getOperand(0); diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h index 179574a73aa01..979c9acbd48e1 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -353,14 +353,13 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo { void storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, - bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; void loadRegFromStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg, + Register VReg, MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; // This tells target independent code that it is okay to pass instructions diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 1b855248bb1fd..351806b0ca3f9 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1694,8 +1694,7 @@ unsigned SIInstrInfo::getVectorRegSpillSaveOpcode( void SIInstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, - bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags) const { MachineFunction *MF = MBB.getParent(); SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>(); @@ -1707,7 +1706,7 @@ void SIInstrInfo::storeRegToStackSlot( MachineMemOperand *MMO = MF->getMachineMemOperand( PtrInfo, MachineMemOperand::MOStore, FrameInfo.getObjectSize(FrameIndex), FrameInfo.getObjectAlign(FrameIndex)); - unsigned SpillSize = TRI->getSpillSize(*RC); + unsigned SpillSize = RI.getSpillSize(*RC); MachineRegisterInfo &MRI = MF->getRegInfo(); if (RI.isSGPRClass(RC)) { @@ -1889,14 +1888,13 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags) const { MachineFunction *MF = MBB.getParent(); SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>(); MachineFrameInfo &FrameInfo = MF->getFrameInfo(); const DebugLoc &DL = MBB.findDebugLoc(MI); - unsigned SpillSize = TRI->getSpillSize(*RC); + unsigned SpillSize = RI.getSpillSize(*RC); MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(*MF, FrameIndex); diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index bd626b1b46891..7f624c4593011 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -302,14 +302,12 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo { void storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, - bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; void loadRegFromStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg, + int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; bool expandPostRAPseudo(MachineInstr &MI) const override; diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index 1a91bbd433553..3375824d6ed05 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -117,27 +117,26 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock, MachineFunction &MF = *SaveBlock.getParent(); const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); - const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); const SIRegisterInfo *RI = ST.getRegisterInfo(); MachineBasicBlock::iterator I = SaveBlock.begin(); - if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) { + if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, RI)) { for (const CalleeSavedInfo &CS : CSI) { // Insert the spill to the stack frame. MCRegister Reg = CS.getReg(); MachineInstrSpan MIS(I, &SaveBlock); - const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass( + const TargetRegisterClass *RC = RI->getMinimalPhysRegClass( Reg, Reg == RI->getReturnAddressReg(MF) ? MVT::i64 : MVT::i32); // If this value was already livein, we probably have a direct use of the // incoming register value, so don't kill at the spill point. This happens // since we pass some special inputs (workgroup IDs) in the callee saved // range. - const bool IsLiveIn = isLiveIntoMBB(Reg, SaveBlock, TRI); + const bool IsLiveIn = isLiveIntoMBB(Reg, SaveBlock, RI); TII.st... [truncated] |
You can test this locally with the following command:git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/include/llvm/CodeGen/TargetInstrInfo.h llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp llvm/lib/CodeGen/InlineSpiller.cpp llvm/lib/CodeGen/RegAllocFast.cpp llvm/lib/CodeGen/RegisterScavenging.cpp llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp llvm/lib/CodeGen/TargetInstrInfo.cpp llvm/lib/Target/AArch64/AArch64InstrInfo.cpp llvm/lib/Target/AArch64/AArch64InstrInfo.h llvm/lib/Target/AMDGPU/SIInstrInfo.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.h llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/lib/Target/ARM/ARMBaseInstrInfo.h llvm/lib/Target/ARM/Thumb1InstrInfo.cpp llvm/lib/Target/ARM/Thumb1InstrInfo.h llvm/lib/Target/ARM/Thumb2InstrInfo.cpp llvm/lib/Target/ARM/Thumb2InstrInfo.h llvm/lib/Target/AVR/AVRInstrInfo.cpp llvm/lib/Target/AVR/AVRInstrInfo.h llvm/lib/Target/BPF/BPFInstrInfo.cpp llvm/lib/Target/BPF/BPFInstrInfo.h llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp llvm/lib/Target/Hexagon/HexagonInstrInfo.h llvm/lib/Target/Lanai/LanaiInstrInfo.cpp llvm/lib/Target/Lanai/LanaiInstrInfo.h llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp llvm/lib/Target/LoongArch/LoongArchInstrInfo.h llvm/lib/Target/MSP430/MSP430InstrInfo.cpp llvm/lib/Target/MSP430/MSP430InstrInfo.h llvm/lib/Target/Mips/Mips16InstrInfo.cpp llvm/lib/Target/Mips/Mips16InstrInfo.h llvm/lib/Target/Mips/MipsInstrInfo.h llvm/lib/Target/Mips/MipsSEFrameLowering.cpp llvm/lib/Target/Mips/MipsSEInstrInfo.cpp llvm/lib/Target/Mips/MipsSEInstrInfo.h llvm/lib/Target/PowerPC/PPCFrameLowering.cpp llvm/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/lib/Target/PowerPC/PPCInstrInfo.h llvm/lib/Target/RISCV/RISCVFrameLowering.cpp llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.h llvm/lib/Target/Sparc/SparcInstrInfo.cpp llvm/lib/Target/Sparc/SparcInstrInfo.h llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp llvm/lib/Target/SystemZ/SystemZInstrInfo.h llvm/lib/Target/VE/VEInstrInfo.cpp llvm/lib/Target/VE/VEInstrInfo.h llvm/lib/Target/X86/X86FastPreTileConfig.cpp llvm/lib/Target/X86/X86FrameLowering.cpp llvm/lib/Target/X86/X86InstrInfo.cpp llvm/lib/Target/X86/X86InstrInfo.h llvm/lib/Target/XCore/XCoreFrameLowering.cpp llvm/lib/Target/XCore/XCoreInstrInfo.cpp llvm/lib/Target/XCore/XCoreInstrInfo.h llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp llvm/lib/Target/Xtensa/XtensaInstrInfo.h --diff_from_common_commit
View the diff from clang-format here.diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index d7668cea9..91ac430e4 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -957,170 +957,148 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MFI.getObjectSize(FI), Alignment); switch (TRI.getSpillSize(*RC)) { - case 2: - if (ARM::HPRRegClass.hasSubClassEq(RC)) { - BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH)) - .addReg(SrcReg, getKillRegState(isKill)) + case 2: + if (ARM::HPRRegClass.hasSubClassEq(RC)) { + BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH)) + .addReg(SrcReg, getKillRegState(isKill)) + .addFrameIndex(FI) + .addImm(0) + .addMemOperand(MMO) + .add(predOps(ARMCC::AL)); + } else + llvm_unreachable("Unknown reg class!"); + break; + case 4: + if (ARM::GPRRegClass.hasSubClassEq(RC)) { + BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12)) + .addReg(SrcReg, getKillRegState(isKill)) + .addFrameIndex(FI) + .addImm(0) + .addMemOperand(MMO) + .add(predOps(ARMCC::AL)); + } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { + BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS)) + .addReg(SrcReg, getKillRegState(isKill)) + .addFrameIndex(FI) + .addImm(0) + .addMemOperand(MMO) + .add(predOps(ARMCC::AL)); + } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) { + BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_P0_off)) + .addReg(SrcReg, getKillRegState(isKill)) + .addFrameIndex(FI) + .addImm(0) + .addMemOperand(MMO) + .add(predOps(ARMCC::AL)); + } else if (ARM::cl_FPSCR_NZCVRegClass.hasSubClassEq(RC)) { + BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_FPSCR_NZCVQC_off)) + .addReg(SrcReg, getKillRegState(isKill)) + .addFrameIndex(FI) + .addImm(0) + .addMemOperand(MMO) + .add(predOps(ARMCC::AL)); + } else + llvm_unreachable("Unknown reg class!"); + break; + case 8: + if (ARM::DPRRegClass.hasSubClassEq(RC)) { + BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD)) + .addReg(SrcReg, getKillRegState(isKill)) + .addFrameIndex(FI) + .addImm(0) + .addMemOperand(MMO) + .add(predOps(ARMCC::AL)); + } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { + if (Subtarget.hasV5TEOps()) { + MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD)); + AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill)); + AddDReg(MIB, SrcReg, ARM::gsub_1, 0); + MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO).add( + predOps(ARMCC::AL)); + } else { + // Fallback to STM instruction, which has existed since the dawn of + // time. + MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA)) + .addFrameIndex(FI) + .addMemOperand(MMO) + .add(predOps(ARMCC::AL)); + AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill)); + AddDReg(MIB, SrcReg, ARM::gsub_1, 0); + } + } else + llvm_unreachable("Unknown reg class!"); + break; + case 16: + if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) { + // Use aligned spills if the stack can be realigned. + if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF)) { + BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64)) .addFrameIndex(FI) - .addImm(0) - .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); - } else - llvm_unreachable("Unknown reg class!"); - break; - case 4: - if (ARM::GPRRegClass.hasSubClassEq(RC)) { - BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12)) + .addImm(16) .addReg(SrcReg, getKillRegState(isKill)) - .addFrameIndex(FI) - .addImm(0) .addMemOperand(MMO) .add(predOps(ARMCC::AL)); - } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { - BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS)) + } else { + BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI) - .addImm(0) .addMemOperand(MMO) .add(predOps(ARMCC::AL)); - } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) { - BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_P0_off)) - .addReg(SrcReg, getKillRegState(isKill)) + } + } else if (ARM::QPRRegClass.hasSubClassEq(RC) && + Subtarget.hasMVEIntegerOps()) { + auto MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::MVE_VSTRWU32)); + MIB.addReg(SrcReg, getKillRegState(isKill)) + .addFrameIndex(FI) + .addImm(0) + .addMemOperand(MMO); + addUnpredicatedMveVpredNOp(MIB); + } else + llvm_unreachable("Unknown reg class!"); + break; + case 24: + if (ARM::DTripleRegClass.hasSubClassEq(RC)) { + // Use aligned spills if the stack can be realigned. + if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) && + Subtarget.hasNEON()) { + BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo)) .addFrameIndex(FI) - .addImm(0) - .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); - } else if (ARM::cl_FPSCR_NZCVRegClass.hasSubClassEq(RC)) { - BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_FPSCR_NZCVQC_off)) + .addImm(16) .addReg(SrcReg, getKillRegState(isKill)) - .addFrameIndex(FI) - .addImm(0) .addMemOperand(MMO) .add(predOps(ARMCC::AL)); - } else - llvm_unreachable("Unknown reg class!"); - break; - case 8: - if (ARM::DPRRegClass.hasSubClassEq(RC)) { - BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD)) - .addReg(SrcReg, getKillRegState(isKill)) + } else { + MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA)) + .addFrameIndex(FI) + .add(predOps(ARMCC::AL)) + .addMemOperand(MMO); + MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill)); + MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0); + AddDReg(MIB, SrcReg, ARM::dsub_2, 0); + } + } else + llvm_unreachable("Unknown reg class!"); + break; + case 32: + if (ARM::QQPRRegClass.hasSubClassEq(RC) || + ARM::MQQPRRegClass.hasSubClassEq(RC) || + ARM::DQuadRegClass.hasSubClassEq(RC)) { + if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) && + Subtarget.hasNEON()) { + // FIXME: It's possible to only store part of the QQ register if the + // spilled def has a sub-register index. + BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo)) .addFrameIndex(FI) - .addImm(0) + .addImm(16) + .addReg(SrcReg, getKillRegState(isKill)) .addMemOperand(MMO) .add(predOps(ARMCC::AL)); - } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { - if (Subtarget.hasV5TEOps()) { - MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD)); - AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill)); - AddDReg(MIB, SrcReg, ARM::gsub_1, 0); - MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO) - .add(predOps(ARMCC::AL)); - } else { - // Fallback to STM instruction, which has existed since the dawn of - // time. - MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA)) - .addFrameIndex(FI) - .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); - AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill)); - AddDReg(MIB, SrcReg, ARM::gsub_1, 0); - } - } else - llvm_unreachable("Unknown reg class!"); - break; - case 16: - if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) { - // Use aligned spills if the stack can be realigned. - if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF)) { - BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64)) - .addFrameIndex(FI) - .addImm(16) - .addReg(SrcReg, getKillRegState(isKill)) - .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); - } else { - BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA)) - .addReg(SrcReg, getKillRegState(isKill)) - .addFrameIndex(FI) - .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); - } - } else if (ARM::QPRRegClass.hasSubClassEq(RC) && - Subtarget.hasMVEIntegerOps()) { - auto MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::MVE_VSTRWU32)); - MIB.addReg(SrcReg, getKillRegState(isKill)) - .addFrameIndex(FI) - .addImm(0) - .addMemOperand(MMO); - addUnpredicatedMveVpredNOp(MIB); - } else - llvm_unreachable("Unknown reg class!"); - break; - case 24: - if (ARM::DTripleRegClass.hasSubClassEq(RC)) { - // Use aligned spills if the stack can be realigned. - if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) && - Subtarget.hasNEON()) { - BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo)) - .addFrameIndex(FI) - .addImm(16) - .addReg(SrcReg, getKillRegState(isKill)) - .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); - } else { - MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), - get(ARM::VSTMDIA)) - .addFrameIndex(FI) - .add(predOps(ARMCC::AL)) - .addMemOperand(MMO); - MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill)); - MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0); - AddDReg(MIB, SrcReg, ARM::dsub_2, 0); - } - } else - llvm_unreachable("Unknown reg class!"); - break; - case 32: - if (ARM::QQPRRegClass.hasSubClassEq(RC) || - ARM::MQQPRRegClass.hasSubClassEq(RC) || - ARM::DQuadRegClass.hasSubClassEq(RC)) { - if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) && - Subtarget.hasNEON()) { - // FIXME: It's possible to only store part of the QQ register if the - // spilled def has a sub-register index. - BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo)) - .addFrameIndex(FI) - .addImm(16) - .addReg(SrcReg, getKillRegState(isKill)) - .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); - } else if (Subtarget.hasMVEIntegerOps()) { - BuildMI(MBB, I, DebugLoc(), get(ARM::MQQPRStore)) - .addReg(SrcReg, getKillRegState(isKill)) - .addFrameIndex(FI) - .addMemOperand(MMO); - } else { - MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), - get(ARM::VSTMDIA)) - .addFrameIndex(FI) - .add(predOps(ARMCC::AL)) - .addMemOperand(MMO); - MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill)); - MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0); - MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0); - AddDReg(MIB, SrcReg, ARM::dsub_3, 0); - } - } else - llvm_unreachable("Unknown reg class!"); - break; - case 64: - if (ARM::MQQQQPRRegClass.hasSubClassEq(RC) && - Subtarget.hasMVEIntegerOps()) { - BuildMI(MBB, I, DebugLoc(), get(ARM::MQQQQPRStore)) + } else if (Subtarget.hasMVEIntegerOps()) { + BuildMI(MBB, I, DebugLoc(), get(ARM::MQQPRStore)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI) .addMemOperand(MMO); - } else if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { + } else { MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA)) .addFrameIndex(FI) .add(predOps(ARMCC::AL)) @@ -1128,16 +1106,36 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill)); MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0); MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0); - MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0); - MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0); - MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0); - MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0); - AddDReg(MIB, SrcReg, ARM::dsub_7, 0); - } else - llvm_unreachable("Unknown reg class!"); - break; - default: + AddDReg(MIB, SrcReg, ARM::dsub_3, 0); + } + } else + llvm_unreachable("Unknown reg class!"); + break; + case 64: + if (ARM::MQQQQPRRegClass.hasSubClassEq(RC) && + Subtarget.hasMVEIntegerOps()) { + BuildMI(MBB, I, DebugLoc(), get(ARM::MQQQQPRStore)) + .addReg(SrcReg, getKillRegState(isKill)) + .addFrameIndex(FI) + .addMemOperand(MMO); + } else if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { + MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA)) + .addFrameIndex(FI) + .add(predOps(ARMCC::AL)) + .addMemOperand(MMO); + MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill)); + MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0); + MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0); + MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0); + MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0); + MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0); + MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0); + AddDReg(MIB, SrcReg, ARM::dsub_7, 0); + } else llvm_unreachable("Unknown reg class!"); + break; + default: + llvm_unreachable("Unknown reg class!"); } } |
s-barannikov approved these changes Sep 12, 2025
RKSimon approved these changes Sep 12, 2025
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LGTM with the clang-format fix
Contributor Author
I'm specifically ignoring that one since it's reformatting the entire large function |
arsenm force-pushed the users/arsenm/codegen/remove-tri-arguments-load-store-stack-slot branch from c138ffb to 426055f Compare arsenm force-pushed the users/arsenm/arm/remove-tri-argument-AddDReg branch 2 times, most recently from 6bde21f to df5d97f Compare arsenm force-pushed the users/arsenm/codegen/remove-tri-arguments-load-store-stack-slot branch 2 times, most recently from 571fa00 to 94cfc2f Compare arsenm force-pushed the users/arsenm/arm/remove-tri-argument-AddDReg branch from df5d97f to bb2322e Compare Base automatically changed from users/arsenm/arm/remove-tri-argument-AddDReg to main November 10, 2025 23:37
This is directly available in TargetInstrInfo
arsenm force-pushed the users/arsenm/codegen/remove-tri-arguments-load-store-stack-slot branch from 94cfc2f to cf4e8e3 Compare arsenm deleted the users/arsenm/codegen/remove-tri-arguments-load-store-stack-slot branch MaskRay added a commit that referenced this pull request Nov 11, 2025
Contributor
| This patch seems to have missed CSKYSubtarget. Seeing failures in our builders. CC: @ilovepi |
Contributor
| Should be fixed by 7911b35 |
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This is directly available in TargetInstrInfo