[PowerPC] Implement paddis #161572
Merged
[PowerPC] Implement paddis #161572
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters. Learn more about bidirectional Unicode characters
| ✅ With the latest revision this PR passed the C/C++ code formatter. |
Member
| @llvm/pr-subscribers-backend-powerpc Author: Lei Huang (lei137) ChangesFull diff: https://github.com/llvm/llvm-project/pull/161572.diff 12 Files Affected:
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index 561a9c51b9cc2..9af61ba74f7d2 100644 --- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -365,10 +365,12 @@ struct PPCOperand : public MCParsedAsmOperand { bool isS16ImmX4() const { return isExtImm<16>(/*Signed*/ true, 4); } bool isS16ImmX16() const { return isExtImm<16>(/*Signed*/ true, 16); } bool isS17Imm() const { return isExtImm<17>(/*Signed*/ true, 1); } - bool isS34Imm() const { + + template <uint64_t N> + bool isSImmExpr() const { // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit // ContextImmediate is needed. - return Kind == Expression || isSImm<34>(); + return Kind == Expression || isSImm<N>(); } bool isS34ImmX16() const { return Kind == Expression || (isSImm<34>() && (getImm() & 15) == 0); diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp index 04b886ae74993..558351b515a2e 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -47,6 +47,9 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) { case PPC::fixup_ppc_half16ds: case PPC::fixup_ppc_half16dq: return Value & 0xfffc; + case PPC::fixup_ppc_pcrel32: + case PPC::fixup_ppc_imm32: + return Value & 0xffffffff; case PPC::fixup_ppc_pcrel34: case PPC::fixup_ppc_imm34: return Value & 0x3ffffffff; @@ -71,6 +74,8 @@ static unsigned getFixupKindNumBytes(unsigned Kind) { case PPC::fixup_ppc_br24abs: case PPC::fixup_ppc_br24_notoc: return 4; + case PPC::fixup_ppc_pcrel32: + case PPC::fixup_ppc_imm32: case PPC::fixup_ppc_pcrel34: case PPC::fixup_ppc_imm34: case FK_Data_8: @@ -154,6 +159,8 @@ MCFixupKindInfo PPCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { {"fixup_ppc_brcond14abs", 16, 14, 0}, {"fixup_ppc_half16", 0, 16, 0}, {"fixup_ppc_half16ds", 0, 14, 0}, + {"fixup_ppc_pcrel32", 0, 32, 0}, + {"fixup_ppc_imm32", 0, 32, 0}, {"fixup_ppc_pcrel34", 0, 34, 0}, {"fixup_ppc_imm34", 0, 34, 0}, {"fixup_ppc_nofixup", 0, 0, 0}}; @@ -166,6 +173,8 @@ MCFixupKindInfo PPCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { {"fixup_ppc_brcond14abs", 2, 14, 0}, {"fixup_ppc_half16", 0, 16, 0}, {"fixup_ppc_half16ds", 2, 14, 0}, + {"fixup_ppc_pcrel32", 0, 32, 0}, + {"fixup_ppc_imm32", 0, 32, 0}, {"fixup_ppc_pcrel34", 0, 34, 0}, {"fixup_ppc_imm34", 0, 34, 0}, {"fixup_ppc_nofixup", 0, 0, 0}}; diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h index df0c666f5b113..4164b697649cd 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h @@ -40,6 +40,12 @@ enum Fixups { /// instrs like 'std'. fixup_ppc_half16ds, + // A 32-bit fixup corresponding to PC-relative paddis. + fixup_ppc_pcrel32, + + // A 32-bit fixup corresponding to Non-PC-relative paddis. + fixup_ppc_imm32, + // A 34-bit fixup corresponding to PC-relative paddi. fixup_ppc_pcrel34, diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp index b27bc3bd49315..a0fb8a9ac9ad1 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp @@ -430,15 +430,15 @@ void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo, printOperand(MI, OpNo, STI, O); } -void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo, +template<uint64_t N> +void PPCInstPrinter::printSImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) { - long long Value = MI->getOperand(OpNo).getImm(); - assert(isInt<34>(Value) && "Invalid s34imm argument!"); - O << (long long)Value; - } - else + int64_t Value = MI->getOperand(OpNo).getImm(); + assert(isInt<N>(Value) && "Invalid imm argument!"); + O << (int64_t)Value; + } else printOperand(MI, OpNo, STI, O); } @@ -532,7 +532,7 @@ void PPCInstPrinter::printMemRegImmHash(const MCInst *MI, unsigned OpNo, void PPCInstPrinter::printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { - printS34ImmOperand(MI, OpNo, STI, O); + printSImmOperand<34>(MI, OpNo, STI, O); O << '('; printImmZeroOperand(MI, OpNo + 1, STI, O); O << ')'; @@ -541,7 +541,7 @@ void PPCInstPrinter::printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo, void PPCInstPrinter::printMemRegImm34(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { - printS34ImmOperand(MI, OpNo, STI, O); + printSImmOperand<34>(MI, OpNo, STI, O); O << '('; printOperand(MI, OpNo + 1, STI, O); O << ')'; diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h index 48f66ca26958e..f68ef240b0387 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h @@ -80,7 +80,8 @@ class PPCInstPrinter : public MCInstPrinter { const MCSubtargetInfo &STI, raw_ostream &O); void printS16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printS34ImmOperand(const MCInst *MI, unsigned OpNo, + template<uint64_t N> + void printSImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printU16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index 81d8e94b660d7..b28304b07e1a3 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -46,6 +46,7 @@ static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset, case PPC::fixup_ppc_br24_notoc: case PPC::fixup_ppc_brcond14: case PPC::fixup_ppc_pcrel34: + case PPC::fixup_ppc_pcrel32: PCRel = true; } Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel)); diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td index 1aefea1a1c498..8a80a95b531aa 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td @@ -284,9 +284,41 @@ class 8RR_XX4Form_XTABC6_P<bits<6> opcode, dag OOL, dag IOL, string asmstr, let Inst{63} = XT{5}; } +class MLS_DForm_R_SI32_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : PI<1, opcode, OOL, IOL, asmstr, itin> { + bits<5> RT; + bits<5> RA; + bits<32> SI; + + let Pattern = pattern; + + // The prefix. + let Inst{6...7} = 2; + let Inst{8} = 0; + let Inst{11} = PCRel; + let Inst{16...31} = SI{31...16}; + + // The instruction. + let Inst{38...42} = RT; + let Inst{43...47} = RA; + let Inst{48...63} = SI{15...0}; +} + +multiclass MLS_DForm_R_SI32_RTA5_p<bits<6> opcode, dag OOL, dag IOL, + dag PCRel_IOL, string asmstr, + InstrItinClass itin> { + def NAME : MLS_DForm_R_SI32_RTA5<opcode, OOL, IOL, !strconcat(asmstr, ", 0"), + itin, []>; + def pc : MLS_DForm_R_SI32_RTA5<opcode, OOL, PCRel_IOL, + !strconcat(asmstr, ", 1"), itin, []>, + isPCRel; +} + //-------------------------- Instruction definitions -------------------------// // Predicate combinations available: // [IsISAFuture] +// [IsISAFuture, PrefixInstrs] // [HasVSX, IsISAFuture] // [HasVSX, PrefixInstrs, IsISAFuture] @@ -296,6 +328,18 @@ let Predicates = [IsISAFuture] in { "$RT, $L, $RA, $RB", []>; } +let Predicates = [IsISAFuture, PrefixInstrs] in { + defm PADDIS : MLS_DForm_R_SI32_RTA5_p<15, (outs gprc:$RT), + (ins gprc_nor0:$RA, s32imm:$SI), + (ins immZero:$RA, s32imm_pcrel:$SI), + "paddis $RT, $RA, $SI", IIC_LdStLFD>; + let Interpretation64Bit = 1, isCodeGenOnly = 1 in + defm PADDIS8 : MLS_DForm_R_SI32_RTA5_p<15, (outs g8rc:$RT), + (ins g8rc_nox0:$RA, s32imm:$SI), + (ins immZero:$RA, s32imm_pcrel:$SI), + "paddis $RT, $RA, $SI", IIC_LdStLFD>; +} + let Predicates = [HasVSX, IsISAFuture] in { let mayLoad = 1 in { def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index 65d0484805b95..3846af853e269 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -808,20 +808,39 @@ def s17imm64 : Operand<i64> { let DecoderMethod = "decodeSImmOperand<16>"; let OperandType = "OPERAND_IMMEDIATE"; } +def PPCS32ImmAsmOperand : AsmOperandClass { + let Name = "S32Imm"; + let PredicateMethod = "isSImmExpr<32>"; + let RenderMethod = "addImmOperands"; +} +def s32imm : Operand<i64> { + let PrintMethod = "printSImmOperand<32>"; + let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_imm32>"; + let ParserMatchClass = PPCS32ImmAsmOperand; + let DecoderMethod = "decodeSImmOperand<32>"; + let OperandType = "OPERAND_IMMEDIATE"; +} +def s32imm_pcrel : Operand<i64> { + let PrintMethod = "printSImmOperand<32>"; + let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_pcrel32>"; + let ParserMatchClass = PPCS32ImmAsmOperand; + let DecoderMethod = "decodeSImmOperand<32>"; + let OperandType = "OPERAND_IMMEDIATE"; +} def PPCS34ImmAsmOperand : AsmOperandClass { let Name = "S34Imm"; - let PredicateMethod = "isS34Imm"; + let PredicateMethod = "isSImmExpr<34>"; let RenderMethod = "addImmOperands"; } def s34imm : Operand<i64> { - let PrintMethod = "printS34ImmOperand"; + let PrintMethod = "printSImmOperand<34>"; let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_imm34>"; let ParserMatchClass = PPCS34ImmAsmOperand; let DecoderMethod = "decodeSImmOperand<34>"; let OperandType = "OPERAND_IMMEDIATE"; } def s34imm_pcrel : Operand<i64> { - let PrintMethod = "printS34ImmOperand"; + let PrintMethod = "printSImmOperand<34>"; let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_pcrel34>"; let ParserMatchClass = PPCS34ImmAsmOperand; let DecoderMethod = "decodeSImmOperand<34>"; @@ -914,7 +933,8 @@ def ptr_rc_nor0 : RegisterOperand<ptr_rc_nor0_by_hwmode> { // New addressing modes with 34 bit immediates. def PPCDispRI34Operand : AsmOperandClass { - let Name = "DispRI34"; let PredicateMethod = "isS34Imm"; + let Name = "DispRI34"; + let PredicateMethod = "isSImmExpr<34>"; let RenderMethod = "addImmOperands"; } def dispRI34 : Operand<iPTR> { diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt index cdfc8ce9e0ca5..bdbfdae6ce944 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt @@ -274,6 +274,12 @@ #CHECK: xvmulhuh 4, 5, 7 0xf0,0x85,0x3b,0xd0 +#CHECK: paddis 10, 12, 1000000000, 0 +0x06,0x00,0x3b,0x9a,0x3d,0x4c,0xca,0x00 + +#CHECK: paddis 10, 0, 1000000000, 1 +0x06,0x10,0x3b,0x9a,0x3d,0x40,0xca,0x00 + #CHECK: xxmulmul 8, 3, 4, 2 0xed,0x03,0x22,0x08 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt index f7e314fc819e4..996ffc6fe4a21 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt @@ -268,6 +268,12 @@ #CHECK: xvmulhuh 4, 5, 7 0xd0,0x3b,0x85,0xf0 +#CHECK: paddis 10, 12, 1000000000, 0 +0x9a,0x3b,0x00,0x06,0x00,0xca,0x4c,0x3d + +#CHECK: paddis 10, 0, 1000000000, 1 +0x9a,0x3b,0x10,0x06,0x00,0xca,0x40,0x3d + #CHECK: xxmulmul 8, 3, 4, 2 0x08,0x22,0x03,0xed diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s index 29fedd7c20646..f7023e65e35f9 100644 --- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s +++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s @@ -387,6 +387,14 @@ #CHECK-BE: xvmulhuh 4, 5, 7 # encoding: [0xf0,0x85,0x3b,0xd0] #CHECK-LE: xvmulhuh 4, 5, 7 # encoding: [0xd0,0x3b,0x85,0xf0] + paddis 10, 12, 1000000000, 0 +#CHECK-BE: paddis 10, 12, 1000000000, 0 # encoding: [0x06,0x00,0x3b,0x9a, +#CHECK-BE-SAME: 0x3d,0x4c,0xca,0x00] + + paddis 10, 0, 1000000000, 1 +#CHECK-BE: paddis 10, 0, 1000000000, 1 # encoding: [0x06,0x10,0x3b,0x9a, +#CHECK-BE-SAME: 0x3d,0x40,0xca,0x00] + xxmulmul 8, 3, 4, 2 #CHECK-BE: xxmulmul 8, 3, 4, 2 # encoding: [0xed,0x03,0x22,0x08] #CHECK-LE: xxmulmul 8, 3, 4, 2 # encoding: [0x08,0x22,0x03,0xed] diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31-errors.s b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31-errors.s index 69cdb5cb75ebb..b78391b24df77 100644 --- a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31-errors.s +++ b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31-errors.s @@ -7,10 +7,10 @@ paddi 1, 1, 32, 1 # CHECK: error: invalid operand for instruction -pld 1, 32(1), 1 +paddis 10, 5, 1000000000, 1 # CHECK: error: invalid operand for instruction -paddi 1, 1, 32, 1 +pld 1, 32(1), 1 # CHECK: error: invalid operand for instruction plbz 1, 32(1), 1 |
lei137 force-pushed the users/lei137/CommonizeGetImmEncoding branch from 805ddff to 0449585 Compare lei137 changed the base branch from users/lei137/CommonizeGetImmEncoding to main 
lei137 commented Oct 31, 2025
| paddis 10, 5, 1000000000, 1 | ||
| | ||
| # CHECK: error: invalid operand for instruction | ||
| paddi 1, 1, 32, 1 |
Contributor Author
There was a problem hiding this comment.
Removing since this is a duplicate of line 7.
Contributor Author
| ping |
Contributor Author
| gentle reminder. |
maryammo reviewed Nov 25, 2025
Contributor
maryammo left a comment
maryammo left a comment There was a problem hiding this comment.
It seems the extended mnemonics are missing? ( i.e plis and psubis)
| | ||
| # CHECK: error: invalid operand for instruction | ||
| pld 1, 32(1), 1 | ||
| paddis 10, 5, 1000000000, 1 |
Contributor
There was a problem hiding this comment.
paddis is ISAFuture instruction but test added to ISA31 errors file.
Contributor Author
There was a problem hiding this comment.
There is actually no need for different versions of these error files since no cpu specific info is needed. The run lines are same as in ppc64-errors.s. I will put up a separate PR to merge the 2 and then update this PR to add the error checking to the combined error file. Thx!
Contributor Author
If it's okay, I will post a separate PR to add those. |
amy-kwan approved these changes Nov 27, 2025
Contributor
amy-kwan left a comment
amy-kwan left a comment There was a problem hiding this comment.
LGTM. Also, I am OK with separate PRs for the extended mnemonics.
maryammo approved these changes Nov 27, 2025
Collaborator
| LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/138/builds/22422 Here is the relevant piece of the build log for the reference |
aahrun pushed a commit to aahrun/llvm-project that referenced this pull request Dec 1, 2025
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
5 participants
Add this suggestion to a batch that can be applied as a single commit. This suggestion is invalid because no changes were made to the code. Suggestions cannot be applied while the pull request is closed. Suggestions cannot be applied while viewing a subset of changes. Only one suggestion per line can be applied in a batch. Add this suggestion to a batch that can be applied as a single commit. Applying suggestions on deleted lines is not supported. You must change the existing code in this line in order to create a valid suggestion. Outdated suggestions cannot be applied. This suggestion has been applied or marked resolved. Suggestions cannot be applied from pending reviews. Suggestions cannot be applied on multi-line comments. Suggestions cannot be applied while the pull request is queued to merge. Suggestion cannot be applied right now. Please check back later.
No description provided.