[PowerPC] Use the same lowering rule for vector rounding instructions

[paperchalice]

They should have the same lowering rule.

[llvmbot]

@llvm/pr-subscribers-backend-powerpc

Author: None (paperchalice)

Changes

They should have the same lowering rule.

---

Full diff: https://github.com/llvm/llvm-project/pull/166307.diff

2 Files Affected:

• (modified) llvm/lib/Target/PowerPC/PPCISelLowering.cpp (+2-2)
• (modified) llvm/test/CodeGen/PowerPC/vec_rounding.ll (+9-1)

diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 17f04d0fd05e8..74f1c72b4c27f 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1033,17 +1033,17 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, // so we can only code-gen them with fpexcept.ignore. setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f64, Custom); setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f32, Custom); + setOperationAction(ISD::STRICT_FNEARBYINT, MVT::v2f64, Custom); + setOperationAction(ISD::STRICT_FNEARBYINT, MVT::v4f32, Custom); setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); - setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); setOperationAction(ISD::FRINT, MVT::v2f64, Legal); setOperationAction(ISD::FROUND, MVT::v2f64, Legal); setOperationAction(ISD::FROUND, MVT::f64, Legal); setOperationAction(ISD::FRINT, MVT::f64, Legal); - setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); setOperationAction(ISD::FRINT, MVT::v4f32, Legal); setOperationAction(ISD::FROUND, MVT::v4f32, Legal); setOperationAction(ISD::FROUND, MVT::f32, Legal); diff --git a/llvm/test/CodeGen/PowerPC/vec_rounding.ll b/llvm/test/CodeGen/PowerPC/vec_rounding.ll index 2f16a435440ff..e0a3291ed4712 100644 --- a/llvm/test/CodeGen/PowerPC/vec_rounding.ll +++ b/llvm/test/CodeGen/PowerPC/vec_rounding.ll @@ -1,4 +1,5 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr6 -mattr=+altivec < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=ppc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=NO-VSX ; Check vector round to single-precision toward -infinity (vrfim) ; instruction generation using Altivec. @@ -81,6 +82,9 @@ define <2 x double> @nearbyint_v2f64(<2 x double> %p) ; CHECK-LABEL: nearbyint_v2f64: ; CHECK: bl nearbyint ; CHECK: bl nearbyint +; NO-VSX-LABEL: nearbyint_v2f64: +; NO-VSX: bl nearbyint +; NO-VSX: bl nearbyint declare <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p) define <4 x double> @nearbyint_v4f64(<4 x double> %p) @@ -93,7 +97,11 @@ define <4 x double> @nearbyint_v4f64(<4 x double> %p) ; CHECK: bl nearbyint ; CHECK: bl nearbyint ; CHECK: bl nearbyint - +; NO-VSX-LABEL: nearbyint_v4f64: +; NO-VSX: bl nearbyint +; NO-VSX: bl nearbyint +; NO-VSX: bl nearbyint +; NO-VSX: bl nearbyint declare <4 x float> @llvm.floor.v4f32(<4 x float> %p) define <4 x float> @floor_v4f32(<4 x float> %p) 

[lei137]

I think this check prefix is confusing. The default here I believe is cpu=pwr7 which supports vsx. So it's more clear if the check string is CHECK-VSX. However line 7 and 8 below hard coded datalayout and triple... I guess the runline will take precedence here but it just makes it confusing. Also, we should have checks for all tests when we add a new runline.

I think to update this tc it's best to put in a NFC patch to first update this test to:

1. put target triple into existing run line and remove lines 7 and 8 below.
2. generate the default checks via update_llc_test_checks.py

[lei137]

Since I had it already: [PowerPC][NFC] auto gen checks vec rounding tests

[tstellar]

I can confirm that this PR fixes the build failure I was seeing.