[BOLT][BTI] Add MCPlusBuilder::updateBTIVariant #167308
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bgergely0 force-pushed the users/bgergely0/bolt-is-bti-landing-pad branch from 57061b6 to f1cc15e Compare bgergely0 force-pushed the users/bgergely0/bolt-update-bti branch from ccf25bb to 8b3ff18 Compare bgergely0 requested review from aaupov, ayermolo, maksfb, paschalis-mpeis, rafaelauler, yota9 and yozhu as code owners 
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| @llvm/pr-subscribers-bolt Author: Gergely Bálint (bgergely0) ChangesChecks if an instruction is BTI, and updates the immediate value to the This can be used in situations when the compiler already inserted a BTI Full diff: https://github.com/llvm/llvm-project/pull/167308.diff 3 Files Affected:
diff --git a/bolt/include/bolt/Core/MCPlusBuilder.h b/bolt/include/bolt/Core/MCPlusBuilder.h index 6760586876d94..660c1c64b06cf 100644 --- a/bolt/include/bolt/Core/MCPlusBuilder.h +++ b/bolt/include/bolt/Core/MCPlusBuilder.h @@ -1884,6 +1884,12 @@ class MCPlusBuilder { llvm_unreachable("not implemented"); } + /// Update operand of BTI instruction. + virtual void updateBTIVariant(MCInst &Inst, bool CouldCall, + bool CouldJump) const { + llvm_unreachable("not implemented"); + } + /// Store \p Target absolute address to \p RegName virtual InstructionListType materializeAddress(const MCSymbol *Target, MCContext *Ctx, diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp index 0cf3db8a6fc2a..cb0a9cc0c12db 100644 --- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp +++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp @@ -2730,6 +2730,14 @@ class AArch64MCPlusBuilder : public MCPlusBuilder { Inst.addOperand(MCOperand::createImm(HintNum)); } + void updateBTIVariant(MCInst &Inst, bool CouldCall, + bool CouldJump) const override { + assert(Inst.getOpcode() == AArch64::HINT && "Not a BTI instruction."); + unsigned HintNum = getBTIHintNum(CouldCall, CouldJump); + Inst.clear(); + Inst.addOperand(MCOperand::createImm(HintNum)); + } + InstructionListType materializeAddress(const MCSymbol *Target, MCContext *Ctx, MCPhysReg RegName, int64_t Addend = 0) const override { diff --git a/bolt/unittests/Core/MCPlusBuilder.cpp b/bolt/unittests/Core/MCPlusBuilder.cpp index 439d72a343ce8..02ecb87b4a5e3 100644 --- a/bolt/unittests/Core/MCPlusBuilder.cpp +++ b/bolt/unittests/Core/MCPlusBuilder.cpp @@ -156,6 +156,8 @@ TEST_P(MCPlusBuilderTester, AArch64_BTI) { ASSERT_EQ(II->getOpcode(), AArch64::HINT); ASSERT_EQ(II->getOperand(0).getImm(), 38); ASSERT_TRUE(BC->MIB->isBTILandingPad(*II, true, true)); + BC->MIB->updateBTIVariant(*II, true, false); + ASSERT_TRUE(BC->MIB->isBTILandingPad(*II, true, false)); MCInst BTIj; BC->MIB->createBTI(BTIj, false, true); @@ -163,6 +165,8 @@ TEST_P(MCPlusBuilderTester, AArch64_BTI) { ASSERT_EQ(II->getOpcode(), AArch64::HINT); ASSERT_EQ(II->getOperand(0).getImm(), 36); ASSERT_TRUE(BC->MIB->isBTILandingPad(*II, false, true)); + BC->MIB->updateBTIVariant(*II, true, true); + ASSERT_TRUE(BC->MIB->isBTILandingPad(*II, true, true)); MCInst BTIc; BC->MIB->createBTI(BTIc, true, false); @@ -170,6 +174,8 @@ TEST_P(MCPlusBuilderTester, AArch64_BTI) { ASSERT_EQ(II->getOpcode(), AArch64::HINT); ASSERT_EQ(II->getOperand(0).getImm(), 34); ASSERT_TRUE(BC->MIB->isBTILandingPad(*II, true, false)); + BC->MIB->updateBTIVariant(*II, false, true); + ASSERT_TRUE(BC->MIB->isBTILandingPad(*II, false, true)); MCInst BTIinvalid; ASSERT_DEATH(BC->MIB->createBTI(BTIinvalid, false, false), |
bgergely0 force-pushed the users/bgergely0/bolt-is-bti-landing-pad branch from f1cc15e to ebaccb2 Compare bgergely0 force-pushed the users/bgergely0/bolt-update-bti branch 2 times, most recently from 43aa2de to 905a5ea Compare bgergely0 force-pushed the users/bgergely0/bolt-is-bti-landing-pad branch 2 times, most recently from d054c47 to ee348f3 Compare bgergely0 force-pushed the users/bgergely0/bolt-update-bti branch from 905a5ea to c668bf8 Compare 
| ✅ With the latest revision this PR passed the C/C++ code formatter. |
bgergely0 force-pushed the users/bgergely0/bolt-update-bti branch from c668bf8 to f155e7b Compare bgergely0 force-pushed the users/bgergely0/bolt-is-bti-landing-pad branch from ee348f3 to 90d940e Compare 
peterwaller-arm approved these changes Nov 24, 2025
bgergely0 force-pushed the users/bgergely0/bolt-update-bti branch from f155e7b to 7c2404b Compare bgergely0 force-pushed the users/bgergely0/bolt-is-bti-landing-pad branch from 90d940e to f4f312b Compare bgergely0 force-pushed the users/bgergely0/bolt-update-bti branch from 7c2404b to ab5b8ea Compare Base automatically changed from users/bgergely0/bolt-is-bti-landing-pad to main November 25, 2025 17:37
Checks if an instruction is BTI, and updates the immediate value to the newly requested variant.
bgergely0 force-pushed the users/bgergely0/bolt-update-bti branch from ab5b8ea to c3f271f Compare tanji-dg pushed a commit to tanji-dg/llvm-project that referenced this pull request Nov 27, 2025
Checks if an instruction is BTI, and updates the immediate value to the newly requested variant. This can be used in situations when the compiler already inserted a BTI landing pad to a location, but BOLT needs to update it to a different variant. Example: br x0 to a location with a BTI c.
GeneraluseAI pushed a commit to GeneraluseAI/llvm-project that referenced this pull request Nov 27, 2025
Checks if an instruction is BTI, and updates the immediate value to the newly requested variant. This can be used in situations when the compiler already inserted a BTI landing pad to a location, but BOLT needs to update it to a different variant. Example: br x0 to a location with a BTI c.
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Checks if an instruction is BTI, and updates the immediate value to the
newly requested variant.
This can be used in situations when the compiler already inserted a BTI
landing pad to a location, but BOLT needs to update it to a different variant.
Example: br x0 to a location with a BTI c.