[VPlan] Fix OpType-mismatch in getFlagsFromIndDesc

[artagnon]

Follow up on a cse OpType-mismatch crash reported due to ef023ca (Reland [VPlan] Expand WidenInt inductions with nuw/nsw), setting the OpType correctly when returning from getFlagsFromIndDesc.

[llvmbot]

@llvm/pr-subscribers-vectorizers

@llvm/pr-subscribers-llvm-transforms

Author: Ramkumar Ramachandra (artagnon)

Changes

Follow up on a cse OpType-mismatch crash reported due to ef023ca (Reland [VPlan] Expand WidenInt inductions with nuw/nsw), setting the OpType correctly when returning from getFlagsFromIndDesc.

---

Full diff: https://github.com/llvm/llvm-project/pull/168560.diff

2 Files Affected:

• (modified) llvm/lib/Transforms/Vectorize/VPlanUtils.h (+1-1)
• (added) llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll (+114)

diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.h b/llvm/lib/Transforms/Vectorize/VPlanUtils.h index 38073380eb54c..f59dd46755b54 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanUtils.h +++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.h @@ -90,7 +90,7 @@ inline VPIRFlags getFlagsFromIndDesc(const InductionDescriptor &ID) { ID.getInductionBinOp())) return VPIRFlags::WrapFlagsTy(OBO->hasNoUnsignedWrap(), OBO->hasNoSignedWrap()); - return {}; + return VPIRFlags::WrapFlagsTy(false, false); } } // namespace vputils diff --git a/llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll b/llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll new file mode 100644 index 0000000000000..89f986b5247b5 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll @@ -0,0 +1,114 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6 +; RUN: opt -p loop-vectorize -force-vector-width=4 -S %s | FileCheck %s + +define void @induction_wrapflags(ptr %p, ptr noalias %q) { +; CHECK-LABEL: define void @induction_wrapflags( +; CHECK-SAME: ptr [[P:%.*]], ptr noalias [[Q:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: br label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE15:.*]] ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 3, i32 6, i32 9, i32 12>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE15]] ] +; CHECK-NEXT: [[VEC_IND1:%.*]] = phi <4 x i32> [ <i32 0, i32 3, i32 6, i32 9>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT16:%.*]], %[[PRED_STORE_CONTINUE15]] ] +; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[VEC_IV:%.*]] = add <4 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1, i64 2, i64 3> +; CHECK-NEXT: [[TMP0:%.*]] = icmp ule <4 x i64> [[VEC_IV]], splat (i64 1) +; CHECK-NEXT: [[TMP1:%.*]] = sext <4 x i32> [[VEC_IND]] to <4 x i64> +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i1> [[TMP0]], i32 0 +; CHECK-NEXT: br i1 [[TMP2]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]] +; CHECK: [[PRED_STORE_IF]]: +; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[TMP1]], i32 0 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP3]] +; CHECK-NEXT: store i8 0, ptr [[TMP4]], align 1 +; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]] +; CHECK: [[PRED_STORE_CONTINUE]]: +; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP0]], i32 1 +; CHECK-NEXT: br i1 [[TMP5]], label %[[PRED_STORE_IF2:.*]], label %[[PRED_STORE_CONTINUE3:.*]] +; CHECK: [[PRED_STORE_IF2]]: +; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i64> [[TMP1]], i32 1 +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP6]] +; CHECK-NEXT: store i8 0, ptr [[TMP7]], align 1 +; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE3]] +; CHECK: [[PRED_STORE_CONTINUE3]]: +; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP0]], i32 2 +; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_STORE_IF4:.*]], label %[[PRED_STORE_CONTINUE5:.*]] +; CHECK: [[PRED_STORE_IF4]]: +; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i64> [[TMP1]], i32 2 +; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP9]] +; CHECK-NEXT: store i8 0, ptr [[TMP10]], align 1 +; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE5]] +; CHECK: [[PRED_STORE_CONTINUE5]]: +; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP0]], i32 3 +; CHECK-NEXT: br i1 [[TMP11]], label %[[PRED_STORE_IF6:.*]], label %[[PRED_STORE_CONTINUE7:.*]] +; CHECK: [[PRED_STORE_IF6]]: +; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i64> [[TMP1]], i32 3 +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP12]] +; CHECK-NEXT: store i8 0, ptr [[TMP13]], align 1 +; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE7]] +; CHECK: [[PRED_STORE_CONTINUE7]]: +; CHECK-NEXT: [[TMP14:%.*]] = sext <4 x i32> [[VEC_IND1]] to <4 x i64> +; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i1> [[TMP0]], i32 0 +; CHECK-NEXT: br i1 [[TMP15]], label %[[PRED_STORE_IF8:.*]], label %[[PRED_STORE_CONTINUE9:.*]] +; CHECK: [[PRED_STORE_IF8]]: +; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i64> [[TMP14]], i32 0 +; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP16]] +; CHECK-NEXT: store i8 0, ptr [[TMP17]], align 1 +; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE9]] +; CHECK: [[PRED_STORE_CONTINUE9]]: +; CHECK-NEXT: [[TMP18:%.*]] = extractelement <4 x i1> [[TMP0]], i32 1 +; CHECK-NEXT: br i1 [[TMP18]], label %[[PRED_STORE_IF10:.*]], label %[[PRED_STORE_CONTINUE11:.*]] +; CHECK: [[PRED_STORE_IF10]]: +; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i64> [[TMP14]], i32 1 +; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP19]] +; CHECK-NEXT: store i8 0, ptr [[TMP20]], align 1 +; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE11]] +; CHECK: [[PRED_STORE_CONTINUE11]]: +; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i1> [[TMP0]], i32 2 +; CHECK-NEXT: br i1 [[TMP21]], label %[[PRED_STORE_IF12:.*]], label %[[PRED_STORE_CONTINUE13:.*]] +; CHECK: [[PRED_STORE_IF12]]: +; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x i64> [[TMP14]], i32 2 +; CHECK-NEXT: [[TMP23:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP22]] +; CHECK-NEXT: store i8 0, ptr [[TMP23]], align 1 +; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE13]] +; CHECK: [[PRED_STORE_CONTINUE13]]: +; CHECK-NEXT: [[TMP24:%.*]] = extractelement <4 x i1> [[TMP0]], i32 3 +; CHECK-NEXT: br i1 [[TMP24]], label %[[PRED_STORE_IF14:.*]], label %[[PRED_STORE_CONTINUE15]] +; CHECK: [[PRED_STORE_IF14]]: +; CHECK-NEXT: [[TMP25:%.*]] = extractelement <4 x i64> [[TMP14]], i32 3 +; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP25]] +; CHECK-NEXT: store i8 0, ptr [[TMP26]], align 1 +; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE15]] +; CHECK: [[PRED_STORE_CONTINUE15]]: +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 12) +; CHECK-NEXT: [[VEC_IND_NEXT16]] = add <4 x i32> [[VEC_IND1]], splat (i32 12) +; CHECK-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: br label %[[EXIT:.*]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] + %ind.1 = phi i32 [ %ind.1.next, %loop ], [ 3, %entry ] + %ind.2 = phi i32 [ %ind.1, %loop ], [ 0, %entry ] + %sext.1 = sext i32 %ind.1 to i64 + %gep.1 = getelementptr i8, ptr %p, i64 %sext.1 + store i8 0, ptr %gep.1 + %sext.2 = sext i32 %ind.2 to i64 + %gep.2 = getelementptr i8, ptr %q, i64 %sext.2 + store i8 0, ptr %gep.2 + %iv.next = add i64 %iv, 1 + %ind.1.next = add i32 %ind.1, 3 + %ec = icmp eq i64 %iv, 1 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} 

[github-actions]

🐧 Linux x64 Test Results

• 186333 tests passed
• 4859 tests skipped

[fhahn]

LGTM, with suggestions for the test.