[GISel] Make assignValueToReg take CCValAssign by const reference.

[topperc]

This was previously passed by value. It used to be passed by non-const reference, but it was changed to value in D110610. I'm not sure why.

[llvmbot]

@llvm/pr-subscribers-backend-arm
@llvm/pr-subscribers-backend-x86
@llvm/pr-subscribers-llvm-globalisel
@llvm/pr-subscribers-backend-aarch64
@llvm/pr-subscribers-backend-amdgpu
@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-backend-m68k

Author: Craig Topper (topperc)

Changes

This was previously passed by value. It used to be passed by non-const reference, but it was changed to value in D110610. I'm not sure why.

---

Full diff: https://github.com/llvm/llvm-project/pull/70086.diff

12 Files Affected:

• (modified) llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h (+4-3)
• (modified) llvm/lib/CodeGen/GlobalISel/CallLowering.cpp (+4-6)
• (modified) llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp (+2-2)
• (modified) llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp (+3-3)
• (modified) llvm/lib/Target/ARM/ARMCallLowering.cpp (+6-6)
• (modified) llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp (+3-3)
• (modified) llvm/lib/Target/M68k/GISel/M68kCallLowering.h (+2-2)
• (modified) llvm/lib/Target/Mips/MipsCallLowering.cpp (+4-4)
• (modified) llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp (+3-3)
• (modified) llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h (+1-1)
• (modified) llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp (+2-2)
• (modified) llvm/lib/Target/X86/GISel/X86CallLowering.cpp (+2-2)

diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h index 6fbcb744e624a81..ec0b3363f516941 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h @@ -268,7 +268,7 @@ class CallLowering { /// handle the appropriate COPY (either to or from) and mark any /// relevant uses/defines as needed. virtual void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) = 0; + const CCValAssign &VA) = 0; /// The specified value has been assigned to a stack /// location. Load or store it there, with appropriate extension @@ -323,11 +323,12 @@ class CallLowering { /// Insert G_ASSERT_ZEXT/G_ASSERT_SEXT or other hint instruction based on \p /// VA, returning the new register if a hint was inserted. - Register buildExtensionHint(CCValAssign &VA, Register SrcReg, LLT NarrowTy); + Register buildExtensionHint(const CCValAssign &VA, Register SrcReg, + LLT NarrowTy); /// Provides a default implementation for argument handling. void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override; + const CCValAssign &VA) override; }; /// Base class for ValueHandlers used for arguments passed to a function call, diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp index 78f019cff5b2f30..975787a8f5e734f 100644 --- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp @@ -1184,9 +1184,8 @@ Register CallLowering::ValueHandler::extendRegister(Register ValReg, void CallLowering::ValueAssigner::anchor() {} -Register CallLowering::IncomingValueHandler::buildExtensionHint(CCValAssign &VA, - Register SrcReg, - LLT NarrowTy) { +Register CallLowering::IncomingValueHandler::buildExtensionHint( + const CCValAssign &VA, Register SrcReg, LLT NarrowTy) { switch (VA.getLocInfo()) { case CCValAssign::LocInfo::ZExt: { return MIRBuilder @@ -1226,9 +1225,8 @@ static bool isCopyCompatibleType(LLT SrcTy, LLT DstTy) { (DstTy.isPointer() && SrcTy.isScalar()); } -void CallLowering::IncomingValueHandler::assignValueToReg(Register ValVReg, - Register PhysReg, - CCValAssign VA) { +void CallLowering::IncomingValueHandler::assignValueToReg( + Register ValVReg, Register PhysReg, const CCValAssign &VA) { const MVT LocVT = VA.getLocVT(); const LLT LocTy(LocVT); const LLT RegTy = MRI.getType(ValVReg); diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp index 02c1ad49c0004ce..2d6cc870f98e77f 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp @@ -158,7 +158,7 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler { } void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override { + const CCValAssign &VA) override { markPhysRegUsed(PhysReg); IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); } @@ -284,7 +284,7 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler { } void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override { + const CCValAssign &VA) override { MIB.addUse(PhysReg, RegState::Implicit); Register ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp index 08bce3b2fc69244..bc5f1703260c384 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp @@ -62,7 +62,7 @@ struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler { } void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override { + const CCValAssign &VA) override { Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); // If this is a scalar return, insert a readfirstlane just in case the value @@ -118,7 +118,7 @@ struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler { } void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override { + const CCValAssign &VA) override { markPhysRegUsed(PhysReg); if (VA.getLocVT().getSizeInBits() < 32) { @@ -231,7 +231,7 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler { } void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override { + const CCValAssign &VA) override { MIB.addUse(PhysReg, RegState::Implicit); Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); diff --git a/llvm/lib/Target/ARM/ARMCallLowering.cpp b/llvm/lib/Target/ARM/ARMCallLowering.cpp index d1987e32f0e0bef..f9d9930cec6d066 100644 --- a/llvm/lib/Target/ARM/ARMCallLowering.cpp +++ b/llvm/lib/Target/ARM/ARMCallLowering.cpp @@ -110,7 +110,7 @@ struct ARMOutgoingValueHandler : public CallLowering::OutgoingValueHandler { } void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override { + const CCValAssign &VA) override { assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); @@ -136,14 +136,14 @@ struct ARMOutgoingValueHandler : public CallLowering::OutgoingValueHandler { std::function<void()> *Thunk) override { assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet"); - CCValAssign VA = VAs[0]; + const CCValAssign &VA = VAs[0]; assert(VA.needsCustom() && "Value doesn't need custom handling"); // Custom lowering for other types, such as f16, is currently not supported if (VA.getValVT() != MVT::f64) return 0; - CCValAssign NextVA = VAs[1]; + const CCValAssign &NextVA = VAs[1]; assert(NextVA.needsCustom() && "Value doesn't need custom handling"); assert(NextVA.getValVT() == MVT::f64 && "Unsupported type"); @@ -283,7 +283,7 @@ struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler { } void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override { + const CCValAssign &VA) override { assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); @@ -312,14 +312,14 @@ struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler { std::function<void()> *Thunk) override { assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet"); - CCValAssign VA = VAs[0]; + const CCValAssign &VA = VAs[0]; assert(VA.needsCustom() && "Value doesn't need custom handling"); // Custom lowering for other types, such as f16, is currently not supported if (VA.getValVT() != MVT::f64) return 0; - CCValAssign NextVA = VAs[1]; + const CCValAssign &NextVA = VAs[1]; assert(NextVA.needsCustom() && "Value doesn't need custom handling"); assert(NextVA.getValVT() == MVT::f64 && "Unsupported type"); diff --git a/llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp b/llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp index feeee198b1d891f..bb63516e957fd5e 100644 --- a/llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp +++ b/llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp @@ -36,7 +36,7 @@ struct M68kOutgoingArgHandler : public CallLowering::OutgoingValueHandler { STI(MIRBuilder.getMF().getSubtarget<M68kSubtarget>()) {} void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override { + const CCValAssign &VA) override { MIB.addUse(PhysReg, RegState::Implicit); Register ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); @@ -127,7 +127,7 @@ bool M68kCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, void M68kIncomingValueHandler::assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) { + const CCValAssign &VA) { MIRBuilder.getMRI()->addLiveIn(PhysReg); MIRBuilder.getMBB().addLiveIn(PhysReg); IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); @@ -160,7 +160,7 @@ Register M68kIncomingValueHandler::getStackAddress(uint64_t Size, } void CallReturnHandler::assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) { + const CCValAssign &VA) { MIB.addDef(PhysReg, RegState::Implicit); MIRBuilder.buildCopy(ValVReg, PhysReg); } diff --git a/llvm/lib/Target/M68k/GISel/M68kCallLowering.h b/llvm/lib/Target/M68k/GISel/M68kCallLowering.h index 9fde508c188457b..7644e6cffbb1bc1 100644 --- a/llvm/lib/Target/M68k/GISel/M68kCallLowering.h +++ b/llvm/lib/Target/M68k/GISel/M68kCallLowering.h @@ -53,7 +53,7 @@ struct M68kIncomingValueHandler : public CallLowering::IncomingValueHandler { private: void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override; + const CCValAssign &VA) override; void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO, @@ -76,7 +76,7 @@ struct CallReturnHandler : public M68kIncomingValueHandler { private: void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override; + const CCValAssign &VA) override; MachineInstrBuilder &MIB; }; diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp index 2c276ffa4aebbc2..b85629021127750 100644 --- a/llvm/lib/Target/Mips/MipsCallLowering.cpp +++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp @@ -93,7 +93,7 @@ class MipsIncomingValueHandler : public CallLowering::IncomingValueHandler { private: void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override; + const CCValAssign &VA) override; Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO, @@ -130,7 +130,7 @@ class CallReturnHandler : public MipsIncomingValueHandler { void MipsIncomingValueHandler::assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) { + const CCValAssign &VA) { markPhysRegUsed(PhysReg); IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); } @@ -200,7 +200,7 @@ class MipsOutgoingValueHandler : public CallLowering::OutgoingValueHandler { private: void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override; + const CCValAssign &VA) override; Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO, @@ -219,7 +219,7 @@ class MipsOutgoingValueHandler : public CallLowering::OutgoingValueHandler { void MipsOutgoingValueHandler::assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) { + const CCValAssign &VA) { Register ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); MIB.addUse(PhysReg, RegState::Implicit); diff --git a/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp b/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp index 2730ee32430df2f..99ecc3fe360d17a 100644 --- a/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp +++ b/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp @@ -36,7 +36,7 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler { : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {} void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override; + const CCValAssign &VA) override; void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO, const CCValAssign &VA) override; @@ -49,7 +49,7 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler { } // namespace void OutgoingArgHandler::assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) { + const CCValAssign &VA) { MIB.addUse(PhysReg, RegState::Implicit); Register ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); @@ -144,7 +144,7 @@ bool PPCCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, void PPCIncomingValueHandler::assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) { + const CCValAssign &VA) { markPhysRegUsed(PhysReg); IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); } diff --git a/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h b/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h index 43152305ff7e0a2..17e8c57e563f839 100644 --- a/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h +++ b/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h @@ -46,7 +46,7 @@ class PPCIncomingValueHandler : public CallLowering::IncomingValueHandler { private: void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override; + const CCValAssign &VA) override; void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO, diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp index ec3825a6f780e62..be1771b19316f96 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp @@ -93,7 +93,7 @@ struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler { } void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override { + const CCValAssign &VA) override { Register ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); MIB.addUse(PhysReg, RegState::Implicit); @@ -165,7 +165,7 @@ struct RISCVIncomingValueHandler : public CallLowering::IncomingValueHandler { } void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override { + const CCValAssign &VA) override { markPhysRegUsed(PhysReg); IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); } diff --git a/llvm/lib/Target/X86/GISel/X86CallLowering.cpp b/llvm/lib/Target/X86/GISel/X86CallLowering.cpp index d1e28a071c99594..e69e77e76e6e7bb 100644 --- a/llvm/lib/Target/X86/GISel/X86CallLowering.cpp +++ b/llvm/lib/Target/X86/GISel/X86CallLowering.cpp @@ -106,7 +106,7 @@ struct X86OutgoingValueHandler : public CallLowering::OutgoingValueHandler { } void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override { + const CCValAssign &VA) override { MIB.addUse(PhysReg, RegState::Implicit); Register ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); @@ -212,7 +212,7 @@ struct X86IncomingValueHandler : public CallLowering::IncomingValueHandler { } void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override { + const CCValAssign &VA) override { markPhysRegUsed(PhysReg); IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); } 

[mshockwave]

LGTM