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@preames preames commented Nov 2, 2023

This fixes a miscompile introduced in the recent #67982, and likely exposed in changes since to infer and leverage the same. No active bug reports as of yet.

This was noticed in #70858 (comment).

This fixes a miscompile introduced in the recent llvm#67982, and likely exposed in changes since to infer and leverage the same. No active bug reports as of yet. This was noticed in llvm#70858 (comment).
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llvmbot commented Nov 2, 2023

@llvm/pr-subscribers-llvm-transforms

Author: Philip Reames (preames)

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This fixes a miscompile introduced in the recent #67982, and likely exposed in changes since to infer and leverage the same. No active bug reports as of yet.

This was noticed in #70858 (comment).


Full diff: https://github.com/llvm/llvm-project/pull/71088.diff

2 Files Affected:

  • (modified) llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (+5-1)
  • (modified) llvm/test/Transforms/InstCombine/zext.ll (+1-1)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index fa6fe9d30abd1b8..30c1565ab44f7a5 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -422,8 +422,12 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, APInt InputDemandedMask = DemandedMask.zextOrTrunc(SrcBitWidth); KnownBits InputKnown(SrcBitWidth); - if (SimplifyDemandedBits(I, 0, InputDemandedMask, InputKnown, Depth + 1)) + if (SimplifyDemandedBits(I, 0, InputDemandedMask, InputKnown, Depth + 1)) { + // For zext nneg, we may have dropped the instruction which made the + // input non-negative. + I->dropPoisonGeneratingFlags(); return I; + } assert(InputKnown.getBitWidth() == SrcBitWidth && "Src width changed?"); Known = InputKnown.zextOrTrunc(BitWidth); assert(!Known.hasConflict() && "Bits known to be one AND zero?"); diff --git a/llvm/test/Transforms/InstCombine/zext.ll b/llvm/test/Transforms/InstCombine/zext.ll index 9dd0d929530b333..4034bc3c531b462 100644 --- a/llvm/test/Transforms/InstCombine/zext.ll +++ b/llvm/test/Transforms/InstCombine/zext.ll @@ -783,7 +783,7 @@ define i64 @evaluate_zexted_const_expr(i1 %c) { ; but the flag on the zext doesn't. define i16 @zext_nneg_flag_drop(i8 %x, i16 %y) { ; CHECK-LABEL: @zext_nneg_flag_drop( -; CHECK-NEXT: [[EXT:%.*]] = zext nneg i8 [[X:%.*]] to i16 +; CHECK-NEXT: [[EXT:%.*]] = zext i8 [[X:%.*]] to i16 ; CHECK-NEXT: [[OR1:%.*]] = or i16 [[EXT]], [[Y:%.*]] ; CHECK-NEXT: [[OR2:%.*]] = or i16 [[OR1]], 128 ; CHECK-NEXT: ret i16 [[OR2]] 
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LGTM

}

; FIXME: This is currently miscompiling as the and gets dropped,
; but the flag on the zext doesn't.
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Drop the FIXME in the line above...

@preames preames merged commit 9593cde into llvm:main Nov 2, 2023
@preames preames deleted the pr-instcombine-zext-nneg-miscompile branch November 2, 2023 18:44
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